MEC1322 Datasheet, PDF (82/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
CLAIMING LPC I/O TRANSACTIONS
The LPC Controller claims an I/O transaction that is targeted for one of its peripherals (also referred to as logical
devices). A Base Address Register has been implemented for each logical device. See Section 5.9.3, "I/O Base Address
Registers (BARs)," on page 91. If one of the addresses programmed in the Logical Device Base Address Registers
matches an LPC I/O address using the following relationship, the LPC Controller will claim the LPC bus cycle:
(LPC Address & ~BAR.MASK) == (BAR.LPC_Address & ~BAR.MASK) && (BAR.Valid == 1)
Note: The LPC Controller’s Base Address register is used to define the Base I/O Address of the Configuration
Port.
FORWARDING I/O TRANSACTIONS
The system host will use I/O transactions to access the Configuration and Runtime registers.
To access the Runtime registers, the host must configure the I/O Base Address Registers (BARs), which are accessible
via the Configuration Port. The Configuration Port, Logical Device Ch, is located at the Base I/O Address programmed
in the BAR Configuration register located at offset 60h.
If the I/O transaction matches the BAR of Logical Device Ch, the transaction will be forwarded to the Configuration Port,
otherwise the transaction will be forwarded to the Runtime Registers of the targeted logical device.
Each Logical Device may have up to 128 Contiguous Runtime Registers. The Runtime Registers are located at a
defined offset from the Logical Device’s base address. The host can directly access these registers with a standard LPC
I/O command.
The Logical Device number for the matching device is located in the Frame field of the BAR.
When matching LPC I/O addresses, the LPC Controller ignores address bits that correspond to ‘1b’ bits in the MASK
field.
For illustration purposes only, lets examine two types of logical devices (these may or may not reside in this design).
Example 1:
The Keyboard Controller (8042 Interface) Base Address Register has 60h in the LPC Address field, the Frame field is
01h, and the MASK field is 04h. Because of the single ‘1b’ bit in MASK, the BAR will match LPC I/O patterns in the form
‘0000_0000_0110_0x00b’, so both 60h and 64h will be matched and claimed by the LPC Controller.
Example 2:
If a standard 16550 UART was located at LPC I/O address 238h, then the UART Receive buffer would appear at
address 238h and the Line Status register at 23Dh. If the BAR for the UART was set to 0238_8047h, then the UART
will be matched at I/O address 238h.
5.8.2.2 Device Memory Transactions
Alternatively, LPC memory transactions can be used to access certain logical devices. The LPC Controller claims a
memory transaction that is targeted for one of these logical devices. A Device Memory Base Address Register has been
implemented for the logical devices listed in Table 5-17, “Device Memory Base Address Register Default Values,” on
page 93.
On every LPC bus Memory access all Base Address Registers are checked in parallel and if any matches the LPC mem-
ory address the MEC1322 claims the bus cycle. The memory address is claimed as described in I/O Transactions
except that the LPC memory cycle address is 32 bits instead of the 16 bit I/O cycle address.
Software should insure that no two BARs map the same LPC memory address. If two BARs do map to the same
address, the BAR_Conflict bit in the Host Bus Error Register is set when an LPC access targeting the BAR Conflict
address. An EC interrupt can be generated.
Each Device Memory BAR is 48 bits wide. The format of each Device Memory BAR is summarized in Device Memory
Base Address Register Format. An LPC memory request is translated by the Device Memory BAR into an 8-bit read or
write transaction on the AHB bus. The 32-bit LPC memory address is translated into a 24-bit AHB address
The Base Address Register Table is itself part of the AHB address space. It resides in the Configuration quadrant of
Logical Device Ch, the LPC Interface.
DS00001719D-page 82
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