MEC1322 Datasheet, PDF (213/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 15-21: BIT DEFINITIONS FOR GIRQ18 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
6
7
8
9
[30:10]
31
MCHP Reserved
MCHP Reserved
MCHP Reserved
MCHP Reserved
Reserved
n/a
MCHP Reserved
MCHP Reserved
MCHP Reserved
MCHP Reserved
Reserved
n/a
N MCHP Reserved
N MCHP Reserved
N MCHP Reserved
N MCHP Reserved
N Reserved
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
15.9.12 GIRQ19
TABLE 15-22: BIT DEFINITIONS FOR GIRQ19 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
0
VCC_PWRGD
1
[30:2]
31
LRESET#
Reserved
n/a
VCC_PWRGD
LRESET#
Reserved
n/a
Y VCC_PWRGD interrupt from pin (see Note 15-2 on
page 215).
Y LRESET# interrupt from pin (see Note 15-2 on page 215).
N Reserved
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
15.9.13 GIRQ20
TABLE 15-23: BIT DEFINITIONS FOR GIRQ20 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[4:0] GPIO[204:200]
GPIO_Event
Y Bits[0:4] are controlled by the GPIO_Events generated by
GPIO200 through GPIO204, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
5
Reserved
Reserved
N Reserved
6
GPIO206
GPIO_Event
Y Bit 6 is controlled by the GPIO_Events generated by
GPIO206.
7
Reserved
Reserved
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
N Reserved
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 213