MEC1322 Datasheet, PDF (93/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^{See Table 5-17, "Device Memory Base Address Register Default Values"}
Bits
Description
Type
Default
Reset
Event
13:8 FRAME
These 6 bits are used to specify a logical device frame number within
a bus. This field is multiplied by 400h to provide the frame address
within the peripheral bus address. In the MEC1322 Frame values for
frames corresponding to logical devices that are not present on the
MEC1322 are invalid.
Note 5-
12
See
Table 5-17
nSIO_R
ESET
7:0 MASK
These bits are used to mask off address bits in the address match
between an LPC memory address and the Host Address field of the
BARs, as described in the following section.
Note 5-
12
See
Table 5-17
nSIO_R
ESET
Note 5-12 The Mask and Frame fields of all logical devices are read-only except for 3h (ACPI EC Channel 0).
5.9.4.2 Device Memory Base Address Register Table
Table 5-17 lists the Base Address Registers for logical devices which have LPC memory access in the MEC1322.
LPC Memory cycle access is controlled by LPC Memory Base Address Registers. LPC Memory BAR registers are
located in LDN Ch (LPC Interface) at AHB base address 400F_3300h starting at the offset shown in Table 5-17.
TABLE 5-17: DEVICE MEMORY BASE ADDRESS REGISTER DEFAULT VALUES
LPC offset in
CR space
Logical Device
Number
Logical Device
Memory BAR Default
Value
LPC Memory Address
C0h
9h
Mailbox
0000_0000_0901h
0000_0000h
C6h
3h
ACPIEC0
0000_0062_0304h
0000_0062h
CCh
4h
ACPIEC1
0000_0066_0407h
0000_0066h
D2h
0h
EMI
0000_0000_000Fh
0000_0000h
Note 1: The VALID, DEVICE, FRAME and MASK fields are as shown in Table 5-16, "I/O Base Address Registers".
5.10 Runtime Registers
The runtime registers listed in Table 5-19, "Runtime Register Summary" are for a single instance of the LPC Interface.
The addresses of each register listed in Table 5-19 are defined as a relative offset to the host “Begin Address” define in
Table 5-2.
TABLE 5-18: RUNTIME REGISTER ADDRESS RANGE TABLE
INSTANCE NAME
LPC Interface
INSTANCE
NUMBER
0
HOST
LPC
ADDRESS
SPACE
LPC I/O
BEGIN ADDRESS
Base I/O Address of
Logical Device Ch
+00h
Note 1: The Begin Address indicates where the first register can be accessed in a particular address space for a
block instance.
2: The LPC Runtime registers are only accessible from the LPC interface and are used to implement the LPC
Configuration Port. They are not accessible by any other Host.
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DS00001719D-page 93