MEC1322 Datasheet, PDF (250/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Note:
The following GPIOs that do not exist in the 128-pin package are configured as inputs and grounded in the
package. Firmware should not attempt to turn those GPIOs into outputs and drive them high, or excessive
current will be consumed.
• GPIO067
• GPIO055
• GPIO210
• GPIO200
• GPIO202
• GPIO201
• GPIO203
• GPIO204
The following GPIOs that do not exist in the 128-pin package are not connected (NC) in the package. These
GPIOs should be configured as inputs and the internal pull-down should be enabled.
• GPIO211
• GPIO123
20.8 Pin Control Registers
Two Pin Control Registers are implemented for each GPIO. The Pin Control Register format is described in Section
20.8.1, "Pin Control Register," on page 250. The Pin Control Register 2 format is described in Section 20.8.2, "Pin
Control Register 2," on page 253. Pin Control Register address offsets and defaults are defined in Table 20-5, “Pin
Control Registers,” on page 245.
20.8.1 PIN CONTROL REGISTER
Offset ^{See Note 20-5}
Bits
31:25 RESERVED
24 GPIO input from pad
Description
Type
RES
R
On reads, Bit [24] reflects the state of GPIO input from the pad
regardless of setting of Bit [10].
Note: This bit is forced high when the selected power well is off
as selected by the Power Gating Signal bits. See bits[3:2].
23:17 RESERVED
16 Alternative GPIO data
If enabled by the Output GPIO Write Enable bit, the Alternative GPIO
data bit determines the level on the GPIO pin when the pin is config-
ured for the GPIO output function.
RES
R/W
Default
-
Note 20-5
Reset
Event
-
VCC1_R
ESET
-
Note 20-5
-
VCC1_R
ESET
On writes:
If enabled via the Output GPIO Write Enable
0: GPIO[x] out = ‘0’
1: GPIO[x] out = ‘1’
Note: If disabled via the Output GPIO Write Enable then the
GPIO[x] out pin is unaffected by writing this bit.
On reads:
Bit [16] returns the last programmed value, not the value on the pin.
15:14 RESERVED
RES
-
-
DS00001719D-page 250
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