MEC1322 Datasheet, PDF (244/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
20.3 Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 20-4: INTERRUPTS
Source
GPIO_Event
Description
Each pin in the GPIO Interface has the ability to generate an interrupt
event. This event may be used as a wake event.
The GPIO Interface can generate an interrupt source event on a high
level, low level, rising edge and falling edge, as configured by the Inter-
rupt Detection (int_det) bits in the Pin Control Register associated with
the GPIO signal function.
Note: The minimum pulse width ensured to generate an inter-
rupt/wakeup event is 5ns.
20.4 Accessing GPIOs
There are two ways to access GPIO output data. Bit [10] is used to determine which GPIO output data bit affects the
GPIO output pin.
• Output GPIO Data
- Outputs to individual GPIO ports are grouped into 32-bit GPIO Output Registers.
• Alternative GPIO data
- Alternatively, each GPIO output port is individually accessible via Bit [16] in the port’s Pin Control Register. On
reads, Bit [16] returns the programmed value, not the value on the pin.
There are two ways to access GPIO input data.
• Input GPIO Data
- Inputs from individual GPIO ports are grouped into 32-bit GPIO Input Registers and always reflect the current
state of the GPIO input from the pad.
• GPIO input from pad
- Alternatively, each GPIO input port is individually accessible via Bit [24] in the port’s Pin Control Register. Bit
[24] always reflects the current state of GPIO input from the pad.
20.5 GPIO Indexing
Each GPIO signal function name consists of a 4-character prefix (“GPIO”) followed by a 3-digit octal-encoded index
number. In the MEC1322 GPIO indexing is done sequentially starting from ‘GPIO000.’
20.6 GPIO Multiplexing Control
Pin multiplexing depends upon the Mux Control bits in the Pin Control Register. There are two Pin Control Registers for
each GPIO signal function.
The MEC1322 Pin Control Register address offsets shown in the following tables depends on the GPIO Index number.
Pin Control Register defaults are also shown in these tables.
Note 1: Pin Control Register 2 default values are not shown in these tables.
2: The GPIO143/RSMRST# pin operates as described in Section 1.6, "Notes for Tables in this Chapter," on
page 39 when it is configured as a GPIO; the RSMRST# function is not a true alternate function. For proper
RSMRST# operation on the pin, the GPIO143 control register must not be changed from the GPIO default
function.
3: The VCC1_RST#/GPIO131 pin cannot be used as a GPIO pin. The input path to the VCC1_RST# logic is
always active and will cause a reset if this pin is set low in GPIO mode.
4: The KSI[7:0] pins have the internal pullups enabled by ROM boot code. Therefore the Pin Control Reg. POR
Value is as follows after the ROM boot code runs:
GPIO043 = 00003001h
GPIO042 = 00003001h
DS00001719D-page 244
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