MEC1322 Datasheet, PDF (63/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^24h
Bits
Description
Type
Default
Reset
Event
7 PS2_2 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-14.
6 PS2_1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-14.
5 PS2_0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-14.
4 MCHP Reserved (Note 3-10)
R/W
0h
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
3 ADC Sleep Enable (Note 3-13)
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
2:0 Reserved
R
Note 3-13
The ADC VREF must be powered down in order to get the lowest deep sleep current. The ADC
VREF Power down bit, ADC_VREF_PD_REF is in the EC Subsystem Registers ADC VREF PD on
page 381.
Note 3-14 The PS2 block will only sleep while the PS2 is disabled or in Rx mode with no traffic on the bus.
3.9.10 EC CLOCK REQUIRED 2 STATUS REGISTER (EC_CLK_REQ2_STS)
Offset ^28h
Bits
31:29 RESERVED
28 MCHP Reserved
Description
Type
RES
R
27 MCHP Reserved
R
26 MCHP Reserved
R
25 LED3 Clock Required
R
0: block does NOT need clocks.
1: block requires clocks.
24 TIMER32_1 Clock Required
R
0: block does NOT need clocks.
1: block requires clocks.
23 TIMER32_0 Clock Required
R
0: block does NOT need clocks.
1: block requires clocks.
Default
Reset
Event
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
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DS00001719D-page 63