MEC1322 Datasheet, PDF (149/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
When the MEC1322 receives a “D1” command followed by data (via the host interface), the on-chip hardware copies
the value of data bit 1 in the received data field to the GATEA20 host latch. At no time during this host-interface trans-
action will PCOBF or the IBF flag (bit 1) in the EC Keyboard Status Register be activated; for example, this host control
of GATEA20 is transparent to firmware, with no consequent degradation of overall system performance. Table 11-9
details the possible GATEA20 sequences and the MEC1322 responses.
An additional level of control flexibility is offered via a memory-mapped synchronous set and reset capability. Any data
written to the SETGA20L Register causes the GATEA20 host latch to be set; any data written to the RSTGA20L Register
causes it to be reset. This control mechanism should be used with caution. It was added to augment the “normal” control
flow as described above, not to replace it. Since the host and the firmware have asynchronous control capability of the
host latch via this mechanism, a potential conflict could arise. Therefore, after using the SETGA20L and RSTGA20L
registers, firmware should read back the GATEA20 status via the GATEA20 Control Register (with SAEN = 0) to confirm
the actual GATEA20 response.
TABLE 11-9: GATEA20 COMMAND/DATA SEQUENCE EXAMPLES
Data
Byte
R/W
D[0:7]
IBF Flag
GATEA20
Comments
1
W
D1
0
0
W
DF
0
1
W
FF
0
1
W
D1
0
0
W
DD
0
1
W
FF
0
1
W
D1
0
1
W
D1
0
0
W
DF
0
1
W
FF
0
1
W
D1
0
1
W
D1
0
0
W
DD
0
1
W
FF
0
1
W
D1
0
1
W
XX**
1
1
W
FF
1
Q
GATEA20 Turn-on Sequence
1
1
Q
GATEA20 Turn-off Sequence
0
0
Q
GATEA20 Turn-on Sequence(*)
Q
1
1
Q
GATEA20 Turn-off Sequence(*)
Q
0
0
Q
Invalid Sequence
Q
Q
Note: The following notes apply:
- All examples assume that the SAEN configuration bit is 0.
- “Q” indicates the bit remains set at the previous state.
- *Not a standard sequence.
- **XX = Anything except D1.
- If multiple data bytes, set IBF and wait at state 0. Let the software know something unusual happened.
- For data bytes, only D[1] is used; all other bits are don't care.
- Host Commands (FF, FE, & D1) do not cause IBF. The method of blocking IBF in Figure 11-4 is the nIOW not
being asserted when FF, FE, & D1 Host commands are written”.
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 149