MEC1322 Datasheet, PDF (92/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
5.9.3.2 Logical Device I/O BAR Description
The following table defines the LPC I/O BAR of each logical device implemented in the design.
TABLE 5-16: I/O BASE ADDRESS REGISTERS
Logical
Device
Offset Number
60h
C
Logical Devices
LPC Interface
(Configuration Port)
Reset Default
002E_0C01
(Note 1)
Base Address Register Bit Field Descriptions
Bits
Bits
Bits
[D31:D16] Bit [D15] Bit [D14] [D13:D8] [D6:D0]
Default
LPC I/O
Host
Address VALID DEVICE FRAME
MASK
002E
0
0
C
1
64h
0
EMI 0
0000_000F
0000
0
0
0
F
68h
7
UART 0
0000_0707
0000
0
0
7
7
78h
1
8042EM
0060_0104
0060
0
0
1
4
88h
3
ACPI EC0
0062_0304
0062
0
0
3
4
8Ch
4
ACPI EC1
0066_0407
0066
0
0
4
7
90h
5
ACPI PM1
0000_0507
0000
0
0
5
7
94h
6
Legacy Port92/GateA20 0092_0600
0092
0
0
6
0
98h
9
Mailbox
0000_0901
0000
0
0
9
1
9Ch
B
RTC
0000_0B3F
0000
0
0
B
3F
Note 1: The default Base I/O Address of the Configuration Port can be relocated by programming the BAR register for
Logical Device Ch (LPC/Configuration Port) at offset 60h.
Note 2: The FRAME and MASK fields for these Legacy devices are not used to determine which LPC I/O addresses to
claim. The address range match is maintained within the blocks themselves.
5.9.4 DEVICE MEMORY BASE ADDRESS REGISTERS
Some Logical Devices have a Memory Base Address Register. These Device Memory BARs are located in blocks of
Configuration Registers in Logical Device 0Ch, in the AHB address range 400F_33C0h through 400F_33FFh. The fol-
lowing table defines the generic format used for all of these registers.
Each Device Memory BAR is 48 bits wide. The format of each Device Memory BAR is summarized in Device Memory
Base Address Register Format. An LPC memory request is translated by the Device Memory BAR into an 8-bit read or
write transaction on the AHB bus. The 32-bit LPC memory address is translated into a 24-bit AHB address
5.9.4.1 Device Memory Base Address Register Format
Offset ^{See Table 5-17, "Device Memory Base Address Register Default Values"}
Bits
Description
47:16 HOST_ADDRESS[31:0]
These 32 bits are used to match LPC memory addresses.
15 VALID
If this bit is 1, the BAR is valid and will participate in LPC matches. If
it is 0 this BAR is ignored.
14 RESERVED
Type
R/W
R/W
RES
Default
Reset
Event
See
Table 5-17
See
Table 5-17
nSIO_R
ESET
nSIO_R
ESET
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DS00001719D-page 92
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