MEC1322 Datasheet, PDF (232/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
19.5 Signal Description
There are no external signals.
19.6 Host Interface
The registers defined for the RTC With Date and DST Adjustment are accessible by the host and EC.
19.7 Power, Clocks and Resets
This section defines the Power, Clock, and Reset parameters of the block.
19.7.1 POWER DOMAINS
TABLE 19-1:
POWER SOURCES
Name
VBAT
VCC1
19.7.2 CLOCKS
Description
This power well sources all of the internal registers and logic in this
block.
This power well sources only bus communication. The block continues
to operate internally while this rail is down.
TABLE 19-2: CLOCKS
Name
32KHz_Clk
19.7.3 RESETS
Description
This 32KHz clock input drives all internal logic, and will be present at all
times that the VBAT well is powered.
TABLE 19-3: RESET SIGNALS
Name
VBAT_POR
RTC_RST
VCC1_RESET
Description
This reset signal is used in the RTC_RST signal to reset all of the
registers and logic in this block. It directly resets the Soft Reset bit in the
RTC Control Register.
This reset signal resets all of the registers and logic in this block, except
for the Soft Reset bit in the RTC Control Register. It is triggered by
VBAT_POR, but can also be triggered by a Soft Reset from the RTC
Control Register.
This reset signal is used to inhibit the bus communication logic, and
isolates this block from VCC1 powered circuitry on-chip. Otherwise it has
no effect on the internal state.
19.8 Interrupts
TABLE 19-4:
SYSTEM INTERRUPTS
Source
Description
RTC
This interrupt source for the SIRQ logic is generated when any of the fol-
lowing events occur:
• Update complete. This is triggered, at 1-second intervals, when the
Time register updates have completed
• Alarm. This is triggered when the alarm value matches the current
time (and date, if used)
• Periodic. This is triggered at the chosen programmable rate
DS00001719D-page 232
 2014 - 2015 Microchip Technology Inc.