MEC1322 Datasheet, PDF (146/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
11.5 Host Interface
The 8042 interface is accessed by host software via a registered interface, as defined in Section 11.13, "Configuration
Registers" and Section 11.14, "Runtime Registers".
11.6 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
11.6.1 POWER DOMAINS
TABLE 11-2: POWER SOURCES
Name
VCC1
11.6.2 CLOCK INPUTS
Description
This Power Well is used to power the registers and logic in this block.
TABLE 11-3: CLOCK INPUTS
Name
1MHz
11.6.3 RESETS
Description
Clock used for the counter in the CPU_RESET circuitry.
TABLE 11-4: RESET SIGNALS
Name
VCC1_RESET
PWRGD
PCI RESET#
nSIO_RESET
Description
This reset is asserted when VCC1 is applied.
This signal is asserted when the main power rail is asserted.
This signal is asserted when LRESET# is asserted.
This signal is asserted when VCC1 is low, PWRGD is low, or LRESET#
is asserted.
11.7 Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 11-5:
KIRQ
MIRQ
SYSTEM INTERRUPTS
Source
Description
This interrupt source for the SIRQ logic, representing a Keyboard inter-
rupt, is generated when the PCOBF status bit is ‘1’.
This interrupt source for the SIRQ logic, representing a Mouse interrupt,
is generated when the AUXOBF status bit is ‘1’.
TABLE 11-6:
8042EM_IBF
EC INTERRUPTS
Source
8042EM_OBF
Description
Interrupt generated by the host writing either data or command to the data
register
Interrupt generated by the host reading either data or aux data from the
data register
11.8 Low Power Modes
The 8042 Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
DS00001719D-page 146
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