MEC1322 Datasheet, PDF (174/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 13-7:
Offset
06h
07h
RUNTIME REGISTERS SUMMARY (CONTINUED)
Register Name
Power Management 2 Control 1 Register
Power Management 2 Control 2 Register
13.11.1 POWER MANAGEMENT 1 STATUS 1 REGISTER
Offset ^00h
Bits
Description
7:0 Reserved
13.11.2 POWER MANAGEMENT 1 STATUS 2 REGISTER
Type
R
Default
-
Reset
Event
-
Offset ^01h
Bits
Description
Type
Default
Reset
Event
7 WAK_STS
R/WC
00h
VCC1_R
This bit can be set or cleared by the EC. The Host writing a one to ^{(Note 13}
this bit can also clear this bit.
-1)
ESET
6:4 Reserved
R
-
-
3 PWRBTNOR_STS
R/WC
00h
VCC1_R
This bit can be set or cleared by the EC to simulate a Power button ^{(Note 13}
override event status if the power is controlled by the EC. The Host
-1)
ESET
writing a one to this bit can also clear this bit. The EC must generate
the associated hardware event under software control.
2 RTC_STS
R/WC
00h
VCC1_R
This bit can be set or cleared by the EC to simulate a RTC status. ^{(Note 13}
ESET
The Host writing a one to this bit can also clear this bit. The EC must ^-1)
generate the associated SCI interrupt under software control.
1 SLPBTN_STS
R/WC
00h
VCC1_R
This bit can be set or cleared by the EC to simulate a Sleep button ^{(Note 13}
status if the sleep state is controlled by the EC. The Host writing a
-1)
ESET
one to this bit can also clear this bit. The EC must generate the
associated SCI interrupt under software control.
0 PWRBTN_STS
R/WC
00h
VCC1_R
This bit can be set or cleared by the EC to simulate a Power button ^{(Note 13}
status if the power is controlled by the EC. The Host writing a one to ^-1)
ESET
this bit can also clear this bit. The EC must generate the associated
SCI interrupt under software control.
Note 13-1 These bits are set/cleared by the EC directly i.e., writing ‘1’ sets the bit and writing ‘0’ clears it. These
bits can also be cleared by the Host software writing a one to this bit position and by VCC1_RESET.
Writing a 0 by the Host has no effect.
13.11.3 POWER MANAGEMENT 1 ENABLE 1 REGISTER
Offset ^02h
Bits
7:0 Reserved
Description
Type
R
Default
-
Reset
Event
-
DS00001719D-page 174
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