MEC1322 Datasheet, PDF (122/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
9.9.6 EC DATA BYTE 1 REGISTER
Offset ^05h
Bits
Description
7:0 EC_DATA_BYTE_1
This is byte 1 of the 32-bit EC Data Register.
9.9.7
Use of the Data Byte registers to access EC memory is defined in
detail in Section 9.8.2, "EC Data Register".
EC DATA BYTE 2 REGISTER
Type
R/W
Offset ^06h
Bits
Description
7:0 EC_DATA_BYTE_2
This is byte 2 of the 32-bit EC Data Register.
9.9.8
Use of the Data Byte registers to access EC memory is defined in
detail in Section 9.8.2, "EC Data Register".
EC DATA BYTE 3 REGISTER
Type
R/W
Offset ^07h
Bits
Description
7:0 EC_DATA_BYTE_3
This is byte 3 (Most Significant Byte) of the 32-bit EC Data Register.
Type
R/W
9.9.9
Use of the Data Byte registers to access EC memory is defined in
detail in Section 9.8.2, "EC Data Register".
INTERRUPT SOURCE LSB REGISTER
Offset ^08h
Bits
Description
Type
7:1 EC_SWI_LSB
EC Software Interrupt Least Significant Bits. These bits are software
interrupt bits that may be set by the EC to notify the host of an event.
The meaning of these bits is dependent on the firmware implemen-
tation.
R/WC
Each bit in this field is cleared when written with a ‘1b’. The ability to
clear the bit can be disabled by the EC if the corresponding bit in the
Host Clear Enable Register is set to ‘0b’. This may be used by firm-
ware for events that cannot be cleared while the event is still active.
Default
0h
Reset
Event
VCC1_R
ESET
Default
0h
Reset
Event
VCC1_R
ESET
Default
0h
Reset
Event
VCC1_R
ESET
Default
0h
Reset
Event
VCC1_R
ESET
DS00001719D-page 122
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