MEC1322 Datasheet, PDF (55/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
3.8 EC-Only Registers
TABLE 3-8: EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address (Note 3-9)
PCR
Note 3-9
0
EC
32-bit internal
4008_0100h
address space
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
TABLE 3-9:
Offset
00h
04h
08h
0Ch
10h
14h
18h
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
POWER, CLOCKS AND RESET VCC1-POWERED REGISTERS SUMMARY
Register Name
Chip Sleep Enable Register (CHIP_SLP_EN)
Chip Clock Required Status Registers (CHIP_CLK_REQ_STS)
EC Sleep Enable Register (EC_SLP_EN)
EC Clock Required Status Registers (EC_CLK_REQ_STS)
Host Sleep Enable Register (HOST_SLP_EN)
Host Clock Required Status Registers (HOST_CLK_REQ)
System Sleep Control Register (SYS_SLP_CNTRL)
Processor Clock Control Register (PROC_CLK_CNTRL)
EC Sleep Enable 2 Register (EC_SLP_EN2)
EC Clock Required 2 Status Register (EC_CLK_REQ2_STS)
Slow Clock Control Register (SLOW_CLK_CNTRL)
Oscillator ID Register (CHIP_OSC_ID)
PCR chip sub-system power reset status (CHIP_PWR_RST_STS)
Chip Reset Enable Register (CHIP_RST_EN)
Host Reset Enable Register (HOST_RST_EN)
EC Reset Enable Register (EC_RST_EN)
EC Reset Enable 2 Register (EC_RST_EN2)
Power Reset Control (PWR_RST_CTRL) Register
Note: All register addresses are naturally aligned on 32-bit boundaries. Offsets for registers that are smaller than
32 bits are reserved and must not be used for any other purpose.
3.9 Sleep Enable and Clock Required Registers
The following are the Sleep Enable and Clock Required registers for the MEC1322.
3.9.1 CHIP SLEEP ENABLE REGISTER (CHIP_SLP_EN)
Offset ^00h
Bits
Description
31:2 RESERVED
1 MCHP Reserved (Note 3-10)
Type
RES
R/W
0 MCHP Reserved (Note 3-10)
R/W
Default
Reset
Event
0h
VCC1_R
ESET
0h
VCC1_R
ESET
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DS00001719D-page 55