MEC1322 Datasheet, PDF (253/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 20-8: EDGE ENABLE AND INTERRUPT DETECTION BITS DEFINITION
Edge
Enable
Interrupt Detection Bits
Selected Function
D7
D6
D5
D4
0
0
0
0
Low Level Sensitive
0
0
0
1
High Level Sensitive
0
0
1
0
Reserved
0
0
1
1
Reserved
0
1
0
0
Interrupt events are disabled
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
1
1
0
1
Rising Edge Triggered
1
1
1
0
Falling Edge Triggered
1
1
1
1
Either edge triggered
Note:
Only edge triggered interrupts can wake up the main ring oscillator. The GPIO must be enabled for edge-
triggered interrupts and the GPIO interrupt must be enabled in the interrupt aggregator in order to wake up
the ring when the ring is shut down.
APPLICATION NOTE: All GPIO interrupt detection configurations default to '0000', which is low level interrupt.
Having interrupt detection enabled will un-gated the clock to the GPIO module whenever the
interrupt is active, which increases power consumption. Interrupt detection should be
disabled when not required to save power; this is especially true for pin interfaces (i.e., LPC).
20.8.2 PIN CONTROL REGISTER 2
Offset ^{See Note 20-5}
Bits
Description
Type
Default
Reset
Event
31:6 RESERVED
5:4 Drive Strength
These bits are used to select the drive strength on the pin.
00 = 2mA
01 = 4mA
10 = 8mA
11 = 12mA
3:1 RESERVED
0 Slew Rate
This bit is used to select the slew rate on the pin.
0 = slow (half frequency)
1 = fast
RES
R/W
-
-
Note 1: on VCC1_R
page 248 ESET
RES
R/W
-
-
0
VCC1_R
ESET
20.8.3 GPIO OUTPUT REGISTERS
If enabled by the Output GPIO Write Enable bit, the GPIO Output bits determine the level on the GPIO pin when the pin
is configured for the GPIO output function.
On writes:
If enabled via the Output GPIO Write Enable
0: GPIO[x] out = ‘0’
1: GPIO[x] out = ‘1’
If disabled via the Output GPIO Write Enable then the GPIO[x] out pin is unaffected by writing this bit.
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 253