MEC1322 Datasheet, PDF (270/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
21.9.8 DMA CHANNEL N INTERRUPT STATUS
Offset ^14h
Bits
Description
7:3 Reserved
2 STATUS_DONE
This is an interrupt source register.
This flags when the DMA Channel has completed a transfer suc-
cessfully on its side.
A completed transfer is defined as when the DMA Channel reaches
its limit; Memory Start Address equals Memory End Address.
A completion due to a Hardware Flow Control Terminate will not
flag this interrupt.
Type
R
R/WC
1=Memory Start Address equals Memory End Address
0=Memory Start Address does not equal Memory End Address
1 STATUS_FLOW_CONTROL
This is an interrupt source register.
This flags when the DMA Channel has encountered a Hardware
Flow Control Request after the DMA Channel has completed the
transfer. This means the Master Device is attempting to overflow the
DMA.
1=Hardware Flow Control is requesting after the transfer has com-
pleted
0=No Hardware Flow Control event
0 STATUS_BUS_ERROR
This is an interrupt source register.
This flags when there is an Error detected over the internal 32-bit
Bus.
R/WC
21.9.9
1: Error detected.
DMA CHANNEL N INTERRUPT ENABLE
Offset ^18h
Bits
Description
7:3 Reserved
2 STATUS_ENABLE_DONE
This is an interrupt enable for DMA Channel Interrupt:Status
Done.
Type
R
R/W
1=Enable Interrupt
0=Disable Interrupt
1 STATUS_ENABLE_FLOW_CONTROL_ERROR
R/W
This is an interrupt enable for DMA Channel Interrupt:Status Flow
Control Error.
1=Enable Interrupt
0=Disable Interrupt
Default
-
0h
Reset
Event
-
RESET
0h
RESET
0h
RESET
Default
-
0h
Reset
Event
-
RESET
0h
RESET
DS00001719D-page 270
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