MEC1322 Datasheet, PDF (157/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^04h
Bits
Description
Type
1 IBF
R
Input Buffer Full. This bit is set to “1” whenever the Host writes data
or a command into the HOST_EC Data / CMD Registerr. When this
bit is set, the EC's 8042EM_IBF interrupt is asserted, if enabled.
When the EC reads the Data/CMD Register, this bit is automatically
reset and the interrupt is cleared.
This bit is not reset when PWRGD is asserted or when the LPC
interface powers down. To clear this bit, firmware must read the EC
Data Register in the EC-Only address space.
0 OBF
R
Output Buffer Full. This bit is set when the EC writes a byte of Data
or AUX Data into the EC_HOST Data / AUX Data Register. When
the Host reads the HOST_EC Data / CMD Register, this bit is auto-
matically cleared by hardware and a 8042EM_OBF interrupt is gen-
erated.
This bit is not reset when PWRGD is asserted or when the LPC
interface powers down. To clear this bit, firmware must read the
Data/CMD Register in the Runtime address space.
Default
0h
Reset
Event
VCC1_R
ESET
0h
VCC1_R
ESET
11.15.4 KEYBOARD CONTROL REGISTER
Offset ^08h
Bits
Description
Type
7 AUXH
R/W
AUX in Hardware.
1=AUXOBF of the Keyboard Status Read Register is set in hardware
by a write to the EC AUX Data Register
0=AUXOBF is not modified in hardware, but can be read and written
by the EC using the EC-Only alias of the EC Keyboard Status
Register
6 UD5
R/W
User-defined data. Readable and writable by the EC when written by
the EC at its EC-only alias.
5 OBFEN
R/W
When this bit is ‘1’, the system interrupt signal KIRQ is driven by the
bit PCOBF and MIRQ is driven by AUXOBF. When this bit is ‘0’, KIRQ
and MIRQ are driven low.
This bit must not be changed when OBF of the status register is equal
to ‘1’.
4:3 UD4
R/W
User-defined data. Readable and writable by the EC when written by
the EC at its EC-only alias.
2 PCOBFEN
R/W
1= reflects the value written to the PCOBF Register
0=PCOBF reflects the status of writes to the EC Data Register
Default
0h
Reset
Event
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
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DS00001719D-page 157