MEC1322 Datasheet, PDF (52/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 3-6: TYPICAL MEC1322 CLOCKS VS. ACPI POWER STATES (CONTINUED)
ACPI Power State
Clock
Name
S0
(FULL
ON)
S1
(POS)
S3
(STR)
S4
(STD)
S5
(Soft
Off)
G3
(MECH
Off)
Description
48 MHz Ring Oscilla-
ON
ON
ON
ON
ON
OFF This clock is powered by
tor
the MEC1322 suspend
supply (VCC1) but may
start and stop as
described in Section 3.7,
"Chip Power Manage-
ment Features," on
page 54 (see also
Note 3-3).
3.6 Resets
TABLE 3-7: DEFINITION OF RESET SIGNALS
Reset
Description
Source
VBAT_POR
VCC1_RESET
PCI RESET#
nSIO_RESET
Internal VBAT Reset signal. This signal is used
to reset VBAT powered registers.
Internal VCC1 Reset signal. This signal is used
to reset VCC1 powered registers.
System reset signal connected to the LPC
LRESET# pin.
Performs a reset when VCC is turned off or
when the system host resets the LPC Interface.
VBAT_POR is a pulse that is asserted at the ris-
ing edge of VCC1GD if the VBAT voltage is
below a nominal 1.25V. VBAT_POR is also
asserted as a level if, while VCC1GD is not
asserted (‘0’), the coin cell is replaced with a
new cell that delivers at least a nominal 1.25V. In
this latter case VBAT_POR is de-asserted when
VCC1GD is asserted. No action is taken if the
coin cell is replaced, or if the VBAT voltage falls
below 1.25 V nominal, while VCC1GD is
asserted.
VCC1_RESET is asserted when VCC1GD is low
and is deasserted when VCC1GD is high. The
VCC1_RST# pin asserted as input will also
cause a VCC1_RESET. A WDT_RESET event
will also cause a VCC1_RESET assertion.
Pin Interface, LRESET# pin. See Note 3-8.
nSIO_RESET is a signal that is asserted if
VCC1GD is low, PWRGD is low, or PCI RESET#
is asserted low and may be deasserted when
these three signals are all high. The iRE-
SET_OUT bit controls the deassertion of
nSIO_RESET. See Note 3-8.
A WDT_RESET event will also cause an
nSIO_RESET assertion.
DS00001719D-page 52
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