MEC1322 Datasheet, PDF (112/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
8.0 RAM AND ROM
SRAM
The 128KBytes SRAM (Code or Data) is allocated as follows:
• 96K Optimized for Code
• 32K Optimized for Data.
Note: 120KBytes are available for application code as follows: 96K Optimized for Code, 24K Optimized for Data.
The distinction between “96KB optimized for instructions” and “32KB optimized for data” SRAMs: is as follows:
The MEC1322 has two blocks of SRAM, one of 96KB and one of 32KB. Both can be used for either instructions or
data. As long as the ARM fetches instructions from one SRAM and does loads and stores to the other, code and data
accesses operate in parallel and there are no wait states. If on the same cycle the ARM fetches an instruction and
does a load or a store to the same SRAM, either the code fetch will be delayed by one cycle or the data access will be
delayed by one cycle. The 96KB SRAM is optimized for instructions, in that if the ARM accesses this SRAM for both
instructions and data on the same cycle, the instruction fetch will complete in one cycle and the load/store will be
delayed for one cycle. The 32KB SRAM is optimized for data, in that if the ARM accesses this SRAM for both
instructions and data on the same cycle, the load/store will complete in once cycle and the instruction fetch will be
delayed for one cycle. In both cases, the SRAM arbiter ensures that the arbitration loser will win on subsequent cycles
and thus will not be locked out of the SRAM indefinitely. User applications, therefore, are free to allocate code and data
anywhere in the 128KB SRAM address space, except that there will be an occasional small performance hit if both
code and data are allocated in the same SRAM.
The application loader in the MEC1322 ROM requires the top 8KB of the 32KB SRAM in order to perform its functions.
The user can therefore load a maximum of 120KB into SRAM using the ROM loader. Once the ROM application loader
has completed its operation, the entire 128KB address space can be allocated to whatever functions, code or data, the
user wishes.
The SRAM is located at EC Base address 00100000h in 32-bit internal address space.
Note: 120KB is available for application code in the address range 00100000h to 0011DFFFh
ROM
The 32KByte Boot ROM is located at EC Base address 00000000h in 32-bit internal address space.
Note: 30KB is available for application code in the address range 00000000h to 000077FFh
The memory map of the RAM and ROM is represented as follows:
DS00001719D-page 112
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