MEC1322 Datasheet, PDF (159/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
11.16 Legacy Port92/GATEA20 Configuration Registers
The registers listed in the Configuration Register Summary table are for a single instance of the Legacy
Port92/GATEA20 logic. The addresses of each register listed in this table are defined as a relative offset to the host
“Base Address” defined in the Configuration Register Base Address Table.
TABLE 11-15: CONFIGURATION BASE ADDRESS TABLE
Block Instance
Instance
Number
Logical
Device
Number
Host
Address Space
Base Address
Port92-Legacy
0
1
LPC
Configuration Port
INDEX = 00h
EC
32-bit internal
address space
400F_1800h
Each Configuration register access through the Host Access Port is via its LDN and its Host Access Port Index. EC
access is a relative offset to the EC Base Address.
TABLE 11-16: CONFIGURATION REGISTER SUMMARY
Offset
Register Name (Mnemonic)
30h
Port 92 Enable Register
11.16.1 PORT 92 ENABLE REGISTER
Offset ^30h
Bits
Description
7:1 Reserved
0 P92_EN
When this bit is ‘1’, the Port92h Register is enabled. When this bit is
‘0’, the Port92h Register is disabled, and Host writes to LPC
address 92h are ignored.
Type
R
R/W
Default
-
0h
Reset
Event
-
PWRGD
and
VCC1_R
ESET
11.17 Legacy Port92/GATEA20 Runtime Registers
The registers listed in the Runtime Register Summary table are for a single instance of the Legacy Port92/GATEA20
logic. The addresses of each register listed in this table are defined as a relative offset to the host “Base Address”
defined in the Runtime Register Base Address Table.
TABLE 11-17: RUNTIME REGISTER BASE ADDRESS TABLE
Block Instance
Instance Number
Host
Address Space
Base Address
Port92-Legacy
0
LPC
I/O
0092h
EC
32-bit address
400F_1800h
space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 11-18: RUNTIME REGISTER SUMMARY
Offset
Register Name (Mnemonic)
0h
Port 92 Register
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