MEC1322 Datasheet, PDF (240/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^0Ch
Bits
Description
4 UPDATE_ENDED_INTERRUPT_FLAG
Type
RC
1=A Time and Date update has completed since the last time this reg-
ister was read. This bit displays status regardless of the Update-
Ended Interrupt Enable bit in Register B. Presentation of this sta-
tus indicates that the Time and Date registers will be valid and sta-
ble for over 999ms
0=A Time and Data update has not completed since the last time this
register was read
This bit is automatically cleared by every Read access to this register.
3:0 Reserved
R
Default
0b
Reset
Event
RTC_R
ST
-
-
19.11.14 REGISTER D
Offset ^0Dh
Bits
Description
7:6 Reserved
5:0 DATE_ALARM
This field, if set to a non-zero value, will inhibit the Alarm interrupt
unless this field matches the contents of the Month register also. If
this field contains 00h (default), it represents a don’t-care, allowing
more frequent alarms.
Type
R
R/W
Default
-
00h
Reset
Event
-
RTC_R
ST
19.11.15 RTC CONTROL REGISTER
Offset ^10h
Bits
7:4 Reserved
3 ALARM_ENABLE
Description
Type
R
R/W
1=Enables the Alarm features
0=Disables the Alarm features
2 Microchip Reserved
R/W
1 SOFT_RESET
R/W
A ‘1’ written to this bit position will trigger the RTC_RST reset, reset-
ting the block and all registers except this one and the Test Register.
This bit is self-clearing at the end of the reset, one cycle of LPC Bus
Clock later, and so requires no waiting.
0 BLOCK_ENABLE
R/W
This bit must be ‘1’ in order for the block to function internally. Regis-
ters may be initialized first, before setting this bit to ‘1’ to start opera-
tion.
Default
-
0b
Reset
Event
-
RTC_R
ST
0b
RTC_R
ST
0b
VBAT_
POR
0b
RTC_R
ST
DS00001719D-page 240
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