MEC1322 Datasheet, PDF (182/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
14.10.2 CONFIGURATION SELECT REGISTER
Offset ^F0h
Bits
7:3 Reserved
2 POLARITY
Description
Type
R
R/W
Default
-
0b
Reset
Event
-
RESET
1=The UART_TX and UART_RX pins functions are inverted
0=The UART_TX and UART_RX pins functions are not inverted
1 POWER
R/W
1b
RESET
1=The RESET reset signal is derived from nSIO_RESET
0=The RESET reset signal is derived from VCC1_RESET
0 CLK_SRC
R/W
0b
RESET
1=The UART Baud Clock is derived from an external clock source
0=The UART Baud Clock is derived from one of the two internal clock
sources
14.11 Runtime Registers
The registers listed in the Runtime Register Summary table are for a single instance of the UART. The addresses of
each register listed in this table are defined as a relative offset to the host “Base Address” defined in Runtime Register
Base Address Table.
TABLE 14-10: RUNTIME REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
UART
0
LPC
I/O
EC
32-bit internal
address space
Base Address (Note 14-1)
Programmed BAR
400F_1C00h
Note 14-1 The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
TABLE 14-11: RUNTIME REGISTER SUMMARY
DLAB
(Note 14-2)
Offset
Register Name (Mnemonic)
0
0
1
1
0
x
x
x
x
x
x
x
Note 14-2
0h
Receive Buffer Register
0h
Transmit Buffer Register
0h
Programmable Baud Rate Generator LSB Register
1h
Programmable Baud Rate Generator MSB Register
1h
Interrupt Enable Register
02h
FIFO Control Register
02h
Interrupt Identification Register
03h
Line Control Register
04h
Modem Control Register
05h
Line Status Register
06h
Modem Status Register
07h
Scratchpad Register
DLAB is bit 7 of the Line Control Register.
DS00001719D-page 182
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