MEC1322 Datasheet, PDF (416/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
FIGURE 38-23: BC-LINK WRITE TIMING
BC_CLK
BC_DAT ^{Bit n-1}
t_OH
t_C
Bit n
t_OS
TABLE 38-21: BC-LINK MASTER TIMING DIAGRAM PARAMETERS
Name
Description
MIN
TYP
MAX Units
t_c(High Speed)
t_OS
t_OH
t_IS
t_IH
High Spec BC Clock Frequency
High Spec BC Clock Period
BC-Link Master DATA output setup time
before rising edge of CLK.
BC-Link Master Data hold time after falling
edge of CLK
BC-Link Master DATA input setup time
before rising edge of CLK.
BC-Link Master DATA input hold time after
rising edge of CLK.
23.5
40.8
15
0
24
41.67
24.5
42.5
t_c-t_OH-
MAX
10
MHz
ns
nsec
nsec
nsec
nsec
Note 1: The BC-Link Master DATA input (t_IH in Table 38-21) must be stable before next rising edge of CLK.
2: The BC-Link Clock frequency is limited by the application usage model (see BC-Link Master Section 31.5,
Signal Description). The BC-Link Clock frequency is controlled by the BC-Link Clock Select Register. The
tc(High Speed) parameter implies both BC-link master and companion devices are located on the same cir-
cuit board and a high speed clock setting is possible.
Note: The timing budget equation is as follows for data from BC-Link slave to master:
Tc > TOD(master-clk) + Tprop(clk) +TOD(slave) + Tprop(slave data) + TIS(master).
DS00001719D-page 416
 2014 - 2015 Microchip Technology Inc.