MEC1322 Datasheet, PDF (123/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^08h
Bits
Description
9.9.10
0 EC_WR
EC Mailbox Write. This bit is set when the EC-to-HOST Mailbox
Register has been written by the EC at offset 01h of the EC-Only
registers.
Note: there is no corresponding mask bit in the Interrupt Mask LSB
Register
INTERRUPT SOURCE MSB REGISTER
Type
R
Offset ^09h
Bits
Description
Type
7:0 EC_SWI_MSB
EC Software Interrupt Most Significant Bits. These bits are software
interrupt bits that may be set by the EC to notify the host of an event.
The meaning of these bits is dependent on the firmware implemen-
tation.
R/WC
9.9.11
Each bit in this field is cleared when written with a ‘1b’. The ability to
clear the bit can be disabled by the EC. if the corresponding bit in the
Host Clear Enable Register is set to ‘0b’. This may be used by firm-
ware for events that cannot be cleared while the event is still active.
INTERRUPT MASK LSB REGISTER
Offset ^0Ah
Bits
Description
7:1 EC_SWI_EN_LSB
EC Software Interrupt Enable Least Significant Bits. Each bit that is
set to ‘1b’ in this field enables the generation of a Host Event inter-
rupt by the corresponding bit in the EC_SWI field in the Interrupt
Source LSB Register.
0 MCHP Reserved
Type
R/W
R/W
9.9.12 INTERRUPT MASK MSB REGISTER
Offset ^0Bh
Bits
Description
7:0 EC_SWI_EN_MSB
EC Software Interrupt Enable Most Significant Bits. Each bit that is
set to ‘1b’ in this field enables the generation of a Host Event inter-
rupt by the corresponding bit in the EC_SWI field in the Interrupt
Source MSB Register.
Type
R/W
Default
0h
Reset
Event
VCC1_R
ESET
Default
0h
Reset
Event
VCC1_R
ESET
Default
0h
Reset
Event
VCC1_R
ESET
0h
VCC1_R
ESET
Default
0h
Reset
Event
VCC1_R
ESET
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DS00001719D-page 123