MEC1322 Datasheet, PDF (209/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 15-15: BIT DEFINITIONS FOR GIRQ12 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
3
I2C3 / SMB3
4
I2C0_0_WK
SMB
SMB
5
I2C0_1_WK
SMB
6
I2C2_0_WK
SMB
7
I2C1_0_WK
SMB
8
I2C3_0_WK
SMB
[30:9]
31
Reserved
n/a
Reserved
n/a
N I2C/SMBus controller 3 interrupt. This interrupt is signaled
when the I2C/SMBus controller 3 asserts its interrupt
request.
Y I2C/SMBus controller 0 (port 0) Wake interrupt. This inter-
rupt is signaled when there is activity on the I2C/SMBus
controller 0 port 0 data pin, I2C0_DAT0 (see Note 15-2 on
page 215).
Y I2C/SMBus controller 0 (port 1) Wake interrupt. This inter-
rupt is signaled when there is activity on the I2C/SMBus
controller 0 port 1 data pin, I2C0_DAT1 (see Note 15-2 on
page 215).
Y I2C/SMBus controller 2 (port 0) Wake interrupt. This inter-
rupt is signaled when there is activity on the I2C/SMBus
controller 2 (port 0) data pin, I2C2_DAT0 (see Note 15-2
on page 215).
Y I2C/SMBus controller 1 (port 0) Wake interrupt. This inter-
rupt is signaled when there is activity on the I2C/SMBus
controller 1 port 0 data pin, I2C1_DAT0 (see Note 15-2 on
page 215).
Y I2C/SMBus controller 3 (port 0) Wake interrupt. This inter-
rupt is signaled when there is activity on the I2C/SMBus
controller 3 port 0 data pin, I2C3_DAT0 (see Note 15-2 on
page 215).
N Reserved
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
15.9.6 GIRQ13
TABLE 15-16: BIT DEFINITIONS FOR GIRQ13 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[15:0]
16
17
18
19
20
21
22
23
24
25
26
27
[30:28]
Reserved
IRQ_DMA0
IRQ_DMA1
IRQ_DMA2
IRQ_DMA3
IRQ_DMA4
IRQ_DMA5
IRQ_DMA6
IRQ_DMA7
IRQ_DMA8
IRQ_DMA9
IRQ_DMA10
IRQ_DMA11
Reserved
Reserved
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
DMA10
DMA11
Reserved
N Reserved
N Direct Memory Access Channel 0
N Direct Memory Access Channel 1
N Direct Memory Access Channel 2
N Direct Memory Access Channel 3
N Direct Memory Access Channel 4
N Direct Memory Access Channel 5
N Direct Memory Access Channel 6
N Direct Memory Access Channel 7
N Direct Memory Access Channel 8
N Direct Memory Access Channel 9
N Direct Memory Access Channel 10
N Direct Memory Access Channel 11
N Reserved
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DS00001719D-page 209