MEC1322 Datasheet, PDF (110/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 7-4:
Table Entry
max + 16
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255
EXCEPTION AND INTERRUPT VECTOR TABLE LAYOUT (CONTINUED)
Exception
Number
Exception
max + 16
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255
NVIC Interrupt #max Vector (Highest-numbered NVIC connection.)
. Table size may (but need not) extend further.
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NVIC Interrupt #239 (Architectural Limit of Exception Table)
7.8 Low Power Modes
The ARM processor low power modes are handled through the Power, Clocks, and Resets registers, not directly through
the ARM core registers. See Section 3.7, "Chip Power Management Features," on page 54.
The ARM processor can enter Sleep or Deep Sleep mode internally. This action will cause an output signal Clock
Required to be turned off, allowing clocks to be stopped from the chip level. However, Clock Required will still be held
active, or set to active, unless all of the following conditions exist:
• No interrupt is pending.
• An input signal Sleep Enable from the chip level is active.
• The Debug JTAG port is inactive (reset or configured not present).
In addition, regardless of the above conditions, a chip-level input signal Force Halt may halt the processor and remove
Clock Required.
7.9 Description
7.9.1 BUS CONNECTIONS
There are three bus connections used from MEC1322 EC block, which are directly related to the IP bus ports. See FIG-
URE 7-1: ARM M4F Based Embedded Controller I/O Block Diagram on page 107.
For the mapping of addresses at the chip level, see Chapter 2.0, "Block Overview," on page 45.
7.9.1.1 Closely Coupled Instruction Fetch Bus
As shown in Figure 7-1, the AHB-Lite ICode port from the IP is converted to a more conventional SRAM memory-style
bus and connected to the on-chip memory resources with routing priority appropriate to Instruction Fetches.
7.9.1.2 Closely Coupled Data Bus
As shown in Figure 7-1, the AHB-Lite DCode port from the IP is converted to a more conventional SRAM memory-style
bus and connected to the on-chip memory resources with routing priority appropriate to fast Data Read/Write accesses.
7.9.1.3 Chip-Level System Bus
As shown in Figure 7-1, the AHB-Lite System port from the IP is converted from AHB-Lite to fully arbitrated multi-master
capability (the AMBA 2 defined AHB bus: see ARM Limited: AMBA® Specification (Rev 2.0), IHI0011A, 13 May 1999).
Using this bus, all addressable on-chip resources are available. The multi-mastering capability supports the Microchip
DMA and EMI features if present, as well as the Bit-Banding feature of the IP itself.
As also shown in Figure 7-1, the Closely-Coupled memory resources are also available through this bus connection
using aliased addresses. This is required in order to allow Bit Banding to be used in these regions, but it also allows
them to be accessed by DMA and other bus masters at the chip level.
APPLICATION NOTE: Registers with properties such as Write-1-to-Clear (W1C), Read-to-Clear and FIFOs need to
be handled with appropriate care when being used with the bit band alias addressing
scheme. Accessing such a register through a bit band alias address will cause the hardware
to perform a read-modify-write, and if a W1C-type bit is set, it will get cleared with such an
access. For example, using a bit band access to the Interrupt Aggregator, including the
Interrupt Enables and Block Interrupt Status to clear an IRQ will clear all active IRQs.
DS00001719D-page 110
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