MEC1322 Datasheet, PDF (210/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 15-16: BIT DEFINITIONS FOR GIRQ13 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
31
n/a
n/a
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
15.9.7 GIRQ14
TABLE 15-17: BIT DEFINITIONS FOR GIRQ14 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[1:0]
2
[30:3]
31
Reserved
IRQ_LPC
Reserved
n/a
Reserved
LPC_INTER-
NAL_ERR
Reserved
n/a
N Reserved
N The LPC_INTERNAL_ERR event is sourced by bit D0 of
the Host Bus Error Register.
N Reserved
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
15.9.8 GIRQ15
TABLE 15-18: BIT DEFINITIONS FOR GIRQ15 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
0
UART_0
UART
1
Reserved
Reserved
2
EMI_0
Host-to-EC
5:3
Reserved
6
ACPI_EC[0] IBF
Reserved
EC_IBF
7
ACPI_EC[0] OBF
EC_OBF
8
ACPI_EC[1] IBF
EC_IBF
9
ACPI_EC[1] OBF
EC_OBF
10 ACPI_PM1_CTL ACPIPM1_CTL
11
ACPIPM1 EN ACPIPM1_EN
12
ACPIPM1 STS ACPIPM1_STS
13
8042EM OBF 8042EM_OBF
14
8042EM IBF
8042EM_IBF
15
MBX
MBX Host-to-EC
N The UART interrupt event output indicates if an interrupt
is pending. See Table 14-13, “Interrupt Control Table,” on
page 186.
N Reserved
N Communication event notifying the embedded controller
that the host has written to the Host-to-EC register.
N Reserved
N EC_IBF interrupt is asserted when the IBF in the STATUS
EC-Register is set to ‘1’.
N EC_OBF interrupt is asserted when the OBF in the STA-
TUS EC-Register is cleared to ‘0’.
N EC_IBF interrupt is asserted when the IBF in the STATUS
EC-Register is set to ‘1’.
N EC_OBF interrupt is asserted when the OBF in the STA-
TUS EC-Register is cleared to ‘0’.
N PM1_CTL2 written by Host
N PM1_EN2 written by Host
N PM1_STS2 written by Host
N Interrupt generated by the host reading either data or aux
data from the data register
N Interrupt generated by the host writing either data or com-
mand to the data register
N Interrupt generated for HOST-to-EC events for writes to
the HOST-to-EC Mailbox Register
DS00001719D-page 210
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