MEC1322 Datasheet, PDF (186/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^02h
Bits
Description
0 IPEND
This bit can be used in either a hardwired prioritized or polled envi-
ronment to indicate whether an interrupt is pending. When bit 0 is a
logic ‘0’ an interrupt is pending and the contents of the IIR may be
used as a pointer to the appropriate internal service routine. When
bit 0 is a logic ‘1’ no interrupt is pending.
Type
R
Default
1h
Reset
Event
RESET
TABLE 14-13: INTERRUPT CONTROL TABLE
FIFO
Mode
Only
Interrupt Identification
Register
Interrupt SET and RESET Functions
Bit 3
0
1
0
Bit 2
0
1
Bit 1
0
1
Bit 0
1
0
0
0
1
0
0
Priority
Level
-
Highest
Second
Third
Fourth
Interrupt Type
Interrupt Source
Interrupt Reset
Control
None
None
-
Receiver Line Sta-
tus
Received Data
Available
Overrun Error, Par-
ity Error, Framing
Error or Break
Interrupt
Receiver Data
Available
Reading the Line
Status Register
Read Receiver Buf-
fer or the FIFO
drops below the
trigger level.
Character Timeout
Indication
Transmitter Hold-
ing Register Empty
MODEM Status
No Characters
Have Been
Removed From or
Input to the RCVR
FIFO during the
last 4 Char times
and there is at least
1 char in it during
this time
Transmitter Hold-
ing Register Empty
Clear to Send or
Data Set Ready or
Ring Indicator or
Data Carrier Detect
Reading the
Receiver Buffer
Register
Reading the IIR
Register (if Source
of Interrupt) or Writ-
ing the Transmitter
Holding Register
Reading the
MODEM Status
Register
DS00001719D-page 186
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