MEC1322 Datasheet, PDF (262/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
21.5.3 RESETS
TABLE 21-6: RESET SIGNALS
Name
VCC1_RESET
RESET
Description
This reset signal resets all of the registers and logic in this block.
This reset is generated if either the VCC1_RESET is asserted or the
SOFT_RESET is asserted.
21.6 Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 21-7:
INTERRUPTS
Source
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
DMA7
DMA8
DMA9
DMA10
DMA11
Description
Direct Memory Access Channel 0
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 1
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 2
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 3
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 4
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 5
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 6
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 7
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 8
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 9
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 10
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 11
This signal is generated by the STATUS_DONE bit.
21.7 Low Power Modes
The Internal DMA Controller may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
When the block is commanded to go to sleep it will place the DMA block into sleep mode only after all transactions on
the DMA have been completed. For Firmware Flow Controlled transactions, the DMA will wait until it hits its terminal
count and clears the Go control bit. For Hardware Flow Control, the DMA will go to sleep after either the terminal count
is hit, or the Master device flags the terminate signal.
21.8 Description
The MEC1322 features a 12 channel DMA controller. The DMA controller can autonomously move data from/to any
DMA capable master device to/from any populated memory location. This mechanism allows hardware IP blocks to
transfer large amounts of data into or out of memory without EC intervention.
The DMA has the following characteristics:
• Data is only moved 1 Data Packet at a time
• Data only moves between devices on the accessible via the internal 32-bit address space
DS00001719D-page 262
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