MEC1322 Datasheet, PDF (418/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
FIGURE 38-25: SPI SETUP AND HOLD TIMES, CLKPOL=0, TCLKPH=0, RCLKPH=0
Setup and Hold Times for
Full-Duplex and Bidrectional Modes
SPCLK
(CLKPOL = 0,
TCLKPH = 0,
RCLKPH = 0)
SPDOUT
SPDIN
T1
T2
T3
FIGURE 38-26: SPI SETUP AND HOLD TIMES, CLKPOL=0, TCLKPH=0, RCLKPH=1
Setup and Hold Times for
Full-Duplex and Bidrectional Modes
SPCLK
(CLKPOL = 0,
TCLKPH = 0,
RCLKPH = 1)
SPDOUT
SPDIN
T1
T2
T3
TABLE 38-23: SPI SETUP AND HOLD TIMES PARAMETERS
NAME
DESCRIPTION
MIN
TYP
T1
Data Output Delay
T2
Data IN Setup Time
10
T3
Data IN Hold Time
0
MAX
5
UNITS
ns
ns
ns
38.17.1 SPI INTERFACE TIMINGS
The following timing diagrams represent a single-byte transfer over the SPI interface using different SPCLK phase set-
tings. Data bits are transmitted in bit order starting with the MSB (LSBF=‘0’) or the LSB (LSBF=‘1’). See the SPI Control
Register for information on the LSBF bit. The CS signal in each diagram is a generic bit-controlled chip select signal
required by most peripheral devices. This signal and additional chip selects can be GPIO controlled. Note that these
timings for Full Duplex Mode are also applicable to Half Duplex (or Bi-directional) mode.
DS00001719D-page 418
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