MEC1322 Datasheet, PDF (89/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 5-13: CONFIGURATION REGISTER ADDRESS RANGE TABLE
Instance NAME
Instance
Number
Host
Address Space
LPC Interface
0
LPC
Configuration Port
0
EC
32-bit internal
address space
Begin Address
(Note 5-8
INDEX = 00h
400F_3300h
Note 5-8
The Begin Address indicates where the first register can be accessed in a particular address space
for a block instance.
TABLE 5-14: CONFIGURATION REGISTER SUMMARY
Register Name
Offset
Size
LPC Activate Register
SIRQ Configuration Register Format
I/O Base Address Registers (BARs)
Device Memory Base Address Registers
30h
8
40h - 4Fh
8
See Table 5-16
32
See Table 5-17
48
Notes
5.9.1 LPC ACTIVATE REGISTER
The LPC Activate Register controls the LPC device itself. The Host can shut down the LPC Logical Device by clearing
the Activate bit, but it cannot restart the LPC interface, since once the LPC interface is inactive the Host has no access
to any registers on the device. The Embedded Controller can set or clear the Activate bit at any time.
Offset ^30h
Bits
Description
7:1 RESERVED
0 ACTIVATE
1= Activate
When this bit is 1, the LPC Logical Device is powered and functional.
0= Deactivate
When this bit is 0, the logical device is powered down and inactive.
Except for the LPC Activate Register itself, clocks to the block are
gated and the LPC Logical Device will permit the ring oscillator to be
shut down (see Section 5.11.4, "EC Clock Control Register," on
page 96). LPC bus output pads will be tri-stated.
Type
RES
R/W
Default
-
0b
Reset
Event
-
VCC1_R
ESET
APPLICATION NOTE: The bit in the LPC Activate Register should not be written ‘0’ to by the Host over LPC.
5.9.2 SERIAL IRQ CONFIGURATION REGISTERS
The LPC Controller implements 16 IRQ channels that may be configured to be asserted by any logical device.
• For a description of the SIRQ Configuration Register format see Table 5-15, “SIRQ Interrupt Configuration Regis-
ter Map,” on page 90.
• For a summary of the SIRQ IRQ Configuration registers implemented see Table 5-16, “I/O Base Address Regis-
ters,” on page 92.
• For a list of the SIRQ sources see Table 5-12, “Logical Device Sirq Routing,” on page 87.
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DS00001719D-page 89