MEC1322 Datasheet, PDF (366/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
The firmware executing on the embedded controller writes to the Debug Data Register to initiate a transfer cycle. At first,
data from the Debug Data Register is shifted into the LSB. Afterwards, it is transmitted at the rate of one byte per transfer
cycle.
Data is transferred in one direction only from the Debug Data Register to the external interface. The data is shifted out
at the clock edge. The clock edge is selected by the EDGE_SEL bit in the Debug Control Register. After being shifted
out, valid data is provided at the opposite edge of the TFDP_CLK. For example, when the EDGE_SEL bit is ‘0’ (default),
valid data is maintained at the falling edge of TFDP_CLK. The Setup Time (to the falling edge of TFDP_CLK) is 10 ns,
minimum. The Hold Time is 1 ns, minimum.
When the Serial Debug Port is inactive, the TFDP_CLK and TFDP_DAT outputs are ‘1.’ The EC Bus Clock clock input
is the transfer clock.
FIGURE 32-3:
DATA TRANSFER
TFDP_CLK
TFDP_DAT
CPU_CLOCK
D0
D1
D2
D3
D4
D5
D6
D7
32.11 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the Trace FIFO Debug Port
(TFDP). The addresses of each register listed in this table are defined as a relative offset to the host “Base Address”
defined in the EC-Only Register Base Address Table.
TABLE 32-5: EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
TFDP Debug Port
0
EC
32-bit internal
address space
Base Address
4000_8C00h
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 32-6:
Offset
00h
04h
EC-ONLY REGISTER SUMMARY
Register Name (Mnemonic)
Debug Data Register
Debug Control Register
32.11.1 DEBUG DATA REGISTER
The Debut Data Register is Read/Write. It always returns the last data written by the TFDP or the power-on default ‘00h’.
Offset ^00h
Bits
Description
7:0 DATA
Debug data to be shifted out on the TFDP Debug port. While data is
being shifted out, the Host Interface will ‘hold-off’ additional writes to
the data register until the transfer is complete.
Type
R/W
Default
00h
Reset
Event
VCC1_R
ESET
DS00001719D-page 366
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