MEC1322 Datasheet, PDF (61/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 3-10: SYSTEM SLEEP CONTROL BIT ENCODING
D2
D1
D0
Wake Latency
(TYP)
Description
0
0
0
0
The Core regulator and the Ring Oscillator remain powered and run-
ning during sleep cycles (SYSTEM HEAVY SLEEP 1) (DEFAULT)
0
1
0
0
The Core regulator remains powered and the Ring oscillator is running
but gated during sleep cycles (SYSTEM HEAVY SLEEP 2)
0
X
1
200us
The Core regulator remains powered and the Ring oscillator is powered
(Note 3-12) down during sleep cycles (SYSTEM HEAVY SLEEP 3)
1
X
1
1ms
The Core regulator is suspended and the Ring oscillator is powered
down during sleep cycles. (SYSTEM DEEPEST SLEEP)
Note 3-12 This is the latency following a wake event until the 48 MHz Ring Oscillator is locked and clocking the
system.
3.9.8 PROCESSOR CLOCK CONTROL REGISTER (PROC_CLK_CNTRL)
Offset ^20h
Bits
Description
31:8 RESERVED
7:0 Processor Clock Divide Value
1: divide 48 MHz Ring Oscillator by 1.
4: divide 48 MHz Ring Oscillator by 4.
16: divide 48 MHz Ring Oscillator by 16.
48: divide 48 MHz Ring Oscillator by 48.
No other values are supported.
Type
RES
R/W
Default
Reset
Event
4h
VCC1_R
ESET
3.9.9 EC SLEEP ENABLE 2 REGISTER (EC_SLP_EN2)
Offset ^24h
Bits
Description
31:29 RESERVED
28 MCHP Reserved (Note 3-10)
27 MCHP Reserved (Note 3-10)
26 MCHP Reserved (Note 3-10)
25 LED3 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
24 TIMER32_1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-11 on page 57.
23 TIMER32_0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-11 on page 57.
Type
RES
R/W
R/W
R/W
R/W
R/W
Default
Reset
Event
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
0h
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 61