MEC1322 Datasheet, PDF (192/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
15.0 EC INTERRUPT AGGREGATOR
15.1 Introduction
The EC Interrupt Aggregator works in conjunction with the processor’s interrupt interface to handle hardware interrupts
and exceptions.
Exceptions are synchronous to instructions, are not maskable, and have higher priority than interrupts. All three excep-
tions - reset, memory error, and instruction error - are hardwired directly to the processor. Interrupts are typically asyn-
chronous and are maskable.
Interrupts classified as wake events can be recognized without a running clock, e.g., while the MEC1322 is in sleep
state.
This chapter focuses on the EC Interrupt Aggregator. Please refer to embedded controller’s documentation for more
information on interrupt and exception handling.
15.2 References
None
15.3 Terminology
None
15.4 Interface
FIGURE 15-1:
BLOCK DIAGRAM OF EC Interrupt Aggregator
Interrupt Sources
31
31
31
GIRQ8 Source
Register
GIRQ9 Source
Register
GIRQ10 Source
Register
31
GIRQ23 Source
Register
Masking
Bits
AOI
AOI
Masking
Bits
AOI
Masking
Bits
16
AOI
Masking
Bits
Processor
DS00001719D-page 192
 2014 - 2015 Microchip Technology Inc.