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| MEC1322 Datasheet, PDF (422/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC | |||
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MEC1322
38.19 JTAG Interface Timing
FIGURE 38-32: JTAG POWER-UP & ASYNCHRONOUS RESET TIMING
VCC1 Power
JTAG_RST#
JTAG_CLK
2.8V
tsu
tpw
fclk
FIGURE 38-33: JTAG SETUP & HOLD PARAMETERS
JTAG_CLK
tOD
tOH
JTAG_TDO
tIS tIH
JTAG_TDI
TABLE 38-25: JTAG INTERFACE TIMING PARAMETERS
Name
Description
MIN
TYP
tsu
JTAG_RST# de-assertion after VCC1 power is
applied
tpw
JTAG_RST# assertion pulse width
fclk
JTAG_CLK frequency (see note)
tOD TDO output delay after falling edge of TCLK.
tOH TDO hold time after falling edge of TCLK
tIS
TDI setup time before rising edge of TCLK.
tIH
TDI hold time after rising edge of TCLK.
5
500
5
1 TCLK - tOD
5
5
Note: fclk is the maximum frequency to access a JTAG Register.
MAX
48
10
Units
ms
nsec
MHz
nsec
nsec
nsec
nsec
DS00001719D-page 422
ï£ 2014 - 2015 Microchip Technology Inc.
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