MEC1322 Datasheet, PDF (109/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
7.7.1 NVIC INTERRUPT INTERFACE
The NVIC interrupt unit can be wired to up to 240 interrupt inputs from the chip level. The interrupts that are actually
connected from the chip level are defined in Table 15-3, “Interrupt Event Aggregator Routing Summary,” on page 195.
All NVIC interrupt inputs can be programmed as either pulse or level triggered. They can also be individually masked,
and individually assigned to their own hardware-managed priority level.
7.7.2 NVIC RELATIONSHIP TO EXCEPTION VECTOR TABLE ENTRIES
The Vector Table consists of 4-byte entries, one per vector. Entry 0 is not a vector, but provides an initial Reset value
for the Main Stack Pointer. Vectors start with the Reset vector, at Entry #1. Entries up through #15 are dedicated for
internal exceptions, and do not involve the NVIC.
NVIC entries in the Vector Table start with Entry #16, so that NVIC Interrupt #0 is at Entry #16, and all NVIC interrupt
numbers are incremented by 16 before accessing the Vector Table.
The number of connections to the NVIC determines the necessary minimum size of the Vector Table, as shown below.
It can extend as far as 256 entries (255 vectors, plus the non-vector entry #0).
A Vector entry is used to load the Program Counter (PC) and the EPSR.T bit. Since the Program Counter only expresses
code addresses in units of two-byte Halfwords, bit[0] of the vector location is used to load the EPSR.T bit instead, select-
ing THUMB mode for exception handling. Bit[0] must be ‘1’ in all vectors, otherwise a UsageFault exception will be
posted (INVSTATE, unimplemented instruction set). If the Reset vector is at fault, the exception posted will be HardFault
instead.
TABLE 7-4:
Table Entry
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
.
.
.
n + 16
.
.
.
EXCEPTION AND INTERRUPT VECTOR TABLE LAYOUT
Exception
Number
Exception
(none)
1
2
3
4
5
6
(none)
(none)
(none)
(none)
11
12
(none)
14
15
16
.
.
.
n + 16
.
.
.
Special Entry for Reset Stack Pointer
Holds Reset Value for the Main Stack Pointer. Not a Vector.
Core Internal Exception Vectors start here
Reset Vector (PC + EPSR.T bit)
NMI (Non-Maskable Interrupt) Vector
HardFault Vector
MemManage Vector
BusFault Vector
UsageFault Vector
(Reserved by ARM Ltd.)
(Reserved by ARM Ltd.)
(Reserved by ARM Ltd.)
(Reserved by ARM Ltd.)
SVCall Vector
Debug Monitor Vector
(Reserved by ARM Ltd.)
PendSV Vector
SysTick Vector
NVIC Interrupt Vectors start here
NVIC Interrupt #0 Vector
.
.
.
NVIC Interrupt #n Vector
.
.
.
 2014 - 2015 Microchip Technology Inc.
DS00001719D-page 109