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MEC1322 Datasheet, PDF (346/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC | |||
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MEC1322
FIGURE 29-3:
PS/2 PORT PHYSICAL LAYER BYTE TRANSMISSION PROTOCOL
PS2CLK CLK 1
CLK2
CLK3
CLK9
CLK10
CLK11
PS2DATA Start Bit
Bit 0
Bit 1
Bit 7
Parity
Stop Bit
TABLE 29-7: PS/2 PORT PHYSICAL LAYER BUS STATES
Data
Clock
State
high
high
Idle
high
low
Communication Inhibited
low
low
Request to Send
29.13 Controlling PS/2 Transactions
PS/2 transfers are controlled by fields in the PS2 Control Register.
The interface is enabled by the PS2_EN bit. Transfers are enabled when PS2_EN is â1â and disabled when PS2_EN is
â0â. If the PS2_EN bit is cleared to â0â while a transfer is in progress but prior to the leading edge (falling edge) of the
10th (parity bit) clock edge, the receive data is discarded (RDATA_RDY remains low). If the PS2_EN bit is cleared fol-
lowing the leading edge of the 10th clock signal, then the receive data is saved in the Receive Register (RDATA_RDY
goes high) assuming no parity error.
The direction of a PS/2 transfer is controlled by the PS2_T/R bit.
29.13.1 RECEIVE
If PS2_T/R is â0â while the PS2 Interface is enabled, the interface is configured to receive data. If while PS2_T/R is â0â
RDATA_RDY is â0â, the channelâs PS2CLK and PS2DAT will float waiting for the external PS/2 device to signal the start
of a transmission. If RDATA_RDY is â1â, the channelâs PS2DAT line will float but its PS2CLK line will be held low, holding
off the peripheral, until the Receive Register is read.
The peripheral initiates a reception by sending a start bit followed by the data bits). After a successful reception, data
are placed in the PS2 Receive Buffer Register, the RDATA_RDY bit in the PS2 Status Register is set and the PS2CLK
line is forced low. Further receive transfers are inhibited until the EC reads the data in the PS2 Receive Buffer Register.
RDATA_RDY is cleared and the PS2CLK line is tri-stated following a read of the PS2 Receive Buffer Register.
The Receive Buffer Register is initialized to FFh after a read or after a Time-out has occurred.
29.13.2 TRANSMIT
If PS2_T/R is â1â while the PS2 Interface is enabled, the interface is configured to transmit data. When the PS2_T/R bit
is written to â1â while the state machine is idle, the channel prepares for a transmission: the interface will drive the PS2-
CLK line low and then float the PS2DAT line, holding this state until a write occurs to the Transmit Register or until the
PS2_T/R bit is cleared. A transmission is started by writing the PS2 Transmit Buffer Register. Writes to the Transmit
Buffer Register are blocked when PS2_EN is â0â, PS2_T/R is â0â or when the transmit state machine is active (the
XMIT_IDLE bit in the PS/2 Status Register is â0â). The transmission of data will not start if there is valid data in the
Receive Data Register (when the status bit RDATA_RDY is â1â). When a transmission is started, the transmission state
machine becomes active (the XMIT_IDLE bit is set to â1â by hardware), the PS2DAT line is driven low and within 80ns
the PS2CLK line floats (externally pulled high by the pull-up resistor).
The transmission terminates either on the 11th clock edge of the transmission or if a Transmit Time-Out error condition
occurs. When the transmission terminates, the PS2_T/R bit is cleared to â0âand the state machine becomes idle, setting
XMIT_IDLE to â1â.
DS00001719D-page 346
ï£ 2014 - 2015 Microchip Technology Inc.
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