MEC1322 Datasheet, PDF (265/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
21.9.1 DMA MAIN CONTROL
Offset ^00h
Bits
Description
7:2 Reserved
1 SOFT_RESET
Soft reset the entire module.
Type
R
W
This bit is self-clearing.
0 ACTIVATE
Enable the blocks operation.
R/WS
21.9.2
1=Enable block. Each individual channel must be enabled separately.
0=Disable all channels.
DMA DATA PACKET
Offset ^04h
Bits
Description
31:0 DATA_PACKET
Debug register that has the data that is stored in the Data Packet.
This data is read data from the currently active transfer source.
Type
R
Default
-
0b
Reset
Event
-
-
0b
RESET
Default
0000h
Reset
Event
-
TABLE 21-10: CHANNEL EC-ONLY REGISTER SUMMARY
Offset
Register Name (Mnemonic)
(Note 21-2)
00h
04h
08h
0Ch
10h
14h
18h
Note 21-2
DMA Channel N Activate
DMA Channel N Memory Start Address
DMA Channel N Memory End Address
DMA Channel N Device Address
DMA Channel N Control
DMA Channel N Interrupt Status
DMA Channel N Interrupt Enable
The letter ‘N’ following DMA Channel indicates the Channel Number. Each Channel implemented will
have these registers to determine that channel’s operation.
21.9.3 DMA CHANNEL N ACTIVATE
Offset ^00h
Bits
Description
7:1 Reserved
0 CHANNEL_ACTIVATE
Enable this channel for operation.
The DMA Main Control:Activate must also be enabled for this chan-
nel to be operational.
Type
R
R/W
Default
-
0h
Reset
Event
-
RESET
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DS00001719D-page 265