MEC1322 Datasheet, PDF (173/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Event
RTC Alarm
Event Bit
RTC_STS
Definition
The ACPI specification requires that the RTC alarm generate a hardware
wake-up event from the sleeping state. The RTC alarm can be enabled as
an SCI event and its status can be determined through bits in the Runtime
Registers. The status bit is software Read/Writable by the EC; the enable
bit is Read-only by the EC.
The RTC_STS bit is set by the Host to enable the generation of an SCI due
to the RTC alarm event. The status bit is set by the EC when the RTC gen-
erates an alarm event and is cleared by the Host writing a ‘1’ to this bit (writ-
ing a ‘0’ has no effect); it can also be cleared by the EC. If the enable bit is
set, the EC will generate an SCI power management event.
Figure 13-2 describes the relationship of PM1 Status and Enable bits to the EC_SCI# pin.
FIGURE 13-2:
EC_SCI# INTERFACE
PM1_STS 2 PM1_EN 2
Register
Register
PWRBTN_STS
SLPBTN_STS
RTC_STS
EC_PM_STS Register
EC_SCI_STS
EC_SCI#
13.11 Runtime Registers
The registers listed in the Runtime Register Summary table are for a single instance of the ACPI PM1 interface. The
addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the
Runtime Register Base Address Table.
TABLE 13-6: RUNTIME REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address
ACPI PM1 Block
0
LPC
I/O
Programmed BAR
Interface
0
EC
32-bit internal
400F_1400h
address space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 13-7: RUNTIME REGISTERS SUMMARY
Offset
00h
01h
02h
03h
04h
05h
Register Name
Power Management 1 Status 1 Register
Power Management 1 Status 2 Register
Power Management 1 Enable 1 Register
Power Management 1 Enable 2 Register
Power Management 1 Control 1 Register
Power Management 1 Control 2 Register
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DS00001719D-page 173