MEC1322 Datasheet, PDF (115/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
9.5 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
9.5.1 POWER DOMAINS
TABLE 9-1: POWER SOURCES
Name
Description
VCC1
The logic and registers implemented in this block reside on this single
power well.
9.5.2 CLOCK INPUTS
This block has no special clocking requirements. Host register accesses are synchronized to the host bus clock and EC
register accesses are synchronized to the EC bus clock, thereby allowing the transactions to complete in one bus clock.
9.5.3 RESETS
TABLE 9-2: RESET SIGNALS
Name
VCC1_RESET
Description
This reset signal resets all the logic and register in this block.
9.6 Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 9-3:
Host Event
EC-to-Host
SYSTEM INTERRUPTS
Source
Description
This interrupt source for the SIRQ logic is generated when any of the
EC_SWI bits are asserted and the corresponding EC_SWI_EN bits are
asserted as well.
This event is also asserted if the host writes the EC-to-HOST Mailbox
Register.
This interrupt source for the SIRQ logic is generated by the host writing
the EC-to-HOST Mailbox Register.
TABLE 9-4:
Host-to-EC
EC INTERRUPTS
Source
Description
Interrupt source for the Interrupt Aggregator, generated by the host writ-
ing the HOST-to-EC Mailbox Register.
9.7 Low Power Modes
The Embedded Memory Interface (EMI) automatically enters low power mode when no transaction target it.
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DS00001719D-page 115