MEC1322 Datasheet, PDF (71/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^44h
Bits
Description
3 ADC Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
2:0 RESERVED
Type
R/W
RES
Default
0h
Reset
Event
VCC1_R
ESET
Note: If a block is configured such that it is to be reset when it goes to sleep, then registers within the block may
not be writable when the block is asleep.
3.9.18 POWER RESET CONTROL (PWR_RST_CTRL) REGISTER
Offset ^48h
Bits
Description
31:1 RESERVED
0 iRESET_OUT
The iRESET_OUT bit is used by firmware to control the internal
nSIO_RESET signal function and the external nRESET_OUT pin.
The external pin nRESET_OUT is always driven by nSIO_RESET.
Firmware can program the state of iRESET_OUT except when the
VCC PWRGD bit is not asserted (‘0’), in which case iRESET_OUT is
‘don’t care’ and nSIO_RESET is asserted (‘0’) (TABLE 3-11:).
Type
RES
R/W
The internal nSIO_RESET signal is asserted when iRESET_OUT is
asserted even if the nRESET_OUT pin is configured as an alternate
function.
The iRESET_OUT bit must be cleared to take the Host out of reset.
Default
Reset
Event
1h
VCC1_R
ESET
TABLE 3-11: iRESET_OUT BIT BEHAVIOR
VCC PWRGD
iRESET_OUT
nSIO_RESET &
nRESET_OUT
Description
0
X
0 (ASSERTED) The iRESET_OUT bit does not affect the state of
nSIO_RESET when VCC PWRGD is not asserted.
1
1
0 (ASSERTED) The iRESET_OUT bit can only be written by firmware
0
1 (NOT
when VCC PWRGD is asserted.
ASSERTED)
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DS00001719D-page 71