MEC1322 Datasheet, PDF (367/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
32.11.2 DEBUG CONTROL REGISTER
Offset ^04h
Bits
Description
7 Reserved
6:4 IP_DELAY
Inter-packet Delay. The delay is in terms of TFDP Debug output
clocks. A value of 0 provides a 1 clock inter-packet period, while a
value of 7 provides 8 clocks between packets:
3:2 DIVSEL
Clock Divider Select. The TFDP Debug output clock is determined
by this field, according to Table 32-7, "TFDP Debug Clocking":
1 EDGE_SEL
Type
R
R/W
R/W
R/W
1= Data is shifted out on the falling edge of the debug clock
0= Data is shifted out on the rising edge of the debug clock (Default)
0 EN
R/W
Enable.
1=Clock enabled
0=Clock is disabled (Default)
Default
-
000b
Reset
Event
-
VCC1_R
ESET
00b
VCC1_R
ESET
0b
VCC1_R
ESET
0b
VCC1_R
ESET
TABLE 32-7: TFDP DEBUG CLOCKING
divsel
TFDP Debug Clock
00
24 MHz
01
12 MHz
10
6 MHz
11
Reserved
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DS00001719D-page 367