MEC1322 Datasheet, PDF (191/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
Offset ^06h
Bits
Description
Type
5 DSR
R
This bit is the complement of the Data Set Ready (nDSR) input. If bit
4 of the MCR is set to logic ‘1’, this bit is equivalent to DTR in the
MCR.
4 CTS
R
This bit is the complement of the Clear To Send (nCTS) input. If bit 4
of the MCR is set to logic ‘1’, this bit is equivalent to nRTS in the
MCR.
3 DCD
R
Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD
input to the chip has changed state.
NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic ‘1’, a MODEM Sta-
tus Interrupt is generated.
2 RI
R
Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI
input has changed from logic ‘0’ to logic ‘1’.
1 DSR
R
Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input
has changed state since the last time the MSR was read.
0 CTS
R
Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to
the chip has changed state since the last time the MSR was read.
Default
0h
Reset
Event
RESET
0h
RESET
0h
RESET
0h
RESET
0h
RESET
0h
RESET
Note:
The Modem Status Register (MSR) only provides the current state of the UART MODEM control lines in
Loopback Mode. The MEC1322 does not support external connections for the MODEM Control inputs
(nCTS, nDSR, nRI and nDCD) or for the four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2).
14.11.12 SCRATCHPAD REGISTER
Offset ^07h
Bits
Description
7:0 SCRATCH
This 8 bit read/write register has no effect on the operation of the
Serial Port. It is intended as a scratchpad register to be used by the
programmer to hold data temporarily.
Type
R/W
Default
0h
Reset
Event
RESET
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DS00001719D-page 191