MEC1322 Datasheet, PDF (226/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
17.9.4 TIMER INT ENABLE REGISTER
Offset ^0Ch
Bits
Description
31:0 Reserved
0 EVENT_INTERRUPT_ENABLE
This is the interrupt enable for the status EVENT_INTERRUPT bit in
the Timer Status Register
Type
R
R/W
Default
-
0h
Reset
Event
-
Tim-
er_Reset
17.9.5 TIMER CONTROL REGISTER
Offset ^10h
Bits
Description
31:16 PRE_SCALE
This is used to divide down the system clock through clock enables
to lower the power consumption of the block and allow slow timers.
Updating this value during operation may result in erroneous clock
enable pulses until the clock divider restarts.
The number of clocks per clock enable pulse is (Value + 1); a setting
of 0 runs at the full clock speed, while a setting of 1 runs at half
speed.
15:8 Reserved
7 HALT
This is a halt bit. This will halt the timer as long as it is active. Once
the halt is inactive, the timer will start from where it left off.
Type
R/W
R
R/W
1=Timer is halted. It stops counting. The clock divider will also be
reset.
0=Timer runs normally
6 RELOAD
R/W
This bit reloads the counter without interrupting it operation. This will
not function if the timer has already completed (when the START bit
in this register is ‘0’). This is used to periodically prevent the timer
from firing when an event occurs. Usage while the timer is off may
result in erroneous behavior.
Default
0h
Reset
Event
Tim-
er_Reset
-
-
0h
Tim-
er_Reset
0h
Tim-
er_Reset
DS00001719D-page 226
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