MEC1322 Datasheet, PDF (214/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 15-23: BIT DEFINITIONS FOR GIRQ20 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[9:8] GPIO[211:210]
GPIO_Event
Y Bits[8:9] are controlled by the GPIO_Events generated by
GPIO210 through GPIO211, respectively.
[11:10] MCHP Reserved MCHP Reserved
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
N/A MCHP Reserved
[30:12]
31
Reserved
n/a
Reserved
n/a
N Reserved
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
15.9.14 GIRQ21
TABLE 15-24: BIT DEFINITIONS FOR GIRQ21 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[1:0]
[30:2]
31
MCHP Reserved
Reserved
n/a
n/a
Reserved
n/a
n/a n/a
N Reserved
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
15.9.15 GIRQ22
TABLE 15-25: BIT DEFINITIONS FOR GIRQ22 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[30:0]
31
Reserved
n/a
Reserved
n/a
N Reserved
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
15.9.16 GIRQ23
TABLE 15-26: BIT DEFINITIONS FOR GIRQ23 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
0
16-bit Timer_0
TIMER_32_x
N This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
DS00001719D-page 214
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