MEC1322 Datasheet, PDF (215/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
TABLE 15-26: BIT DEFINITIONS FOR GIRQ23 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
1
16-bit Timer_1
TIMER_32_x
N This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
2
16-bit Timer_2
TIMER_32_x
N This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
3
16-bit Timer_3
TIMER_32_x
N This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
4
32-bit Timer_0
TIMER_32_x
N This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
5
32-bit Timer_1
TIMER_32_x
N This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
[30:6]
Reserved
Reserved
N Reserved
31
n/a
n/a
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
Note 15-2 All wakeup interrupts associated with pins must be configured as falling edge interrupts through the
associated GPIO control register.
15.9.17 BLOCK ENABLE SET REGISTER
Offset
POWER
BIT
TYPE
BIT NAME
BIT
TYPE
BIT NAME
BIT
TYPE
BIT NAME
BIT
TYPE
BIT NAME
200h
VCC1
D31
R
D23
R/WS
D15
R/WS
D7
R
D30
R
D22
R/WS
D14
R/WS
D6
R
32-bit
0000_0000h
D29
D28
D27
D26
R
R
R
R
Reserved
D21
D20
D19
D18
R/WS R/WS R/WS R/WS
IRQ Vector Enable Set [23:16]
D13
R/WS
D12
R/WS
D11
R/WS
D10
R/WS
IRQ Vector Enable Set [15:8]
D5
D4
D3
D2
R
R
R
R
Reserved
Size
VCC1_RESET
Default
D25
D24
R
R
D17
R/WS
D16
R/WS
D9
R/WS
D8
R/WS
D1
D0
R
R
IRQ Vector Enable Set [31:0]
Each IRQ Vector can be individually enabled to assert an interrupt event to the EC.
0= Writing a zero has no effect.
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DS00001719D-page 215