MEC1322 Datasheet, PDF (2/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
• Four EC-based SMBus 2.0 Host Controllers
- Allows Master or Dual Slave Operation
- Controllers are Fully Operational on Standby
Power
- DMA-driven I²C Network Layer Hardware
- I²C Datalink Compatibility Mode
- Multi-Master Capable
- Supports Clock Stretching
- Programmable Bus Speeds
- 400 KHz Fast-mode Capable
- 1 Mbps Fast-mode Plus Capable
- Hardware Bus Access "Fairness" Interface
- SMBus Time-outs Interface
- 5 Ports
- 2 Port Flexible Multiplexing
• PECI 3.0 Interface
• Keyboard Matrix Scan Interface
- 18 x 8 Interrupt/Wake Capable Multiplexed
Keyboard Scan Matrix
- Row Predrive Option
• Four Breathing/Blinking LED Interfaces
- Programmable Blink Rates
- Piecewise Linear Breathing LED Output Con-
troller
- Operational in EC Sleep States
• Dual Fan Tachometer Inputs
• RPM-Based Fan Speed Control Algorithm
- Utilizes one TACH input and one PWM output
- 3% accurate from 500 RPM to 16k RPM
- Automatic Tachometer feedback
- Aging Fan or Invalid Drive Detection
- Spin Up Routine
- Ramp Rate Control
- RPM-based Fan Speed Control Algorithm
• Fast GATEA20 & Fast CPU_RESET
• RSMRST# Functionality Supporting System Deep
Sleep
- Compatible with south bridge SUS-
CLK/RSMRST# gating rules
- Replacement 32K distribution available when
RSMRST# is asserted
• Integrated Power-on Reset Generator
- VCC1_RST# open drain output
- Accepts External driven Reset
• Anti-Glitch Protection on Power-on
• All Blocks Support Low Power Sleep Modes
• General Purpose Input/Output Pins
- Low Power
- High Configurability
• Two pin Debug Port with standard 16C550A regis-
ter interface
- Accessible from both Host and EC
• BC-Link Interconnection Bus
- One High Speed Bus Master Controller
• Package Options
- 128-pin VTQFP
- 132-pin DQFN
- 144-pin WFBGA
Description
The MEC1322 incorporates a high-performance 32-bit
ARM^® Cortex^®-M4 embedded microcontroller with 128
Kilobytes of SRAM and 32 Kilobytes of Boot ROM. It
communicates with the system host using the Intel^®
Low Pin Count (LPC) bus.
The MEC1322 has two SPI memory interfaces that
allow the EC to read its code from external SPI flash
memory: private SPI and/or shared SPI. The Shared
SPI interface allows for EC code to be stored in a
shared SPI chip along with the system BIOS. The pri-
vate SPI memory interface provides for a dedicated
SPI flash that is only accessible by the EC.
The MEC1322 provides support for loading EC code
from the private or shared SPI flash device on a VCC1
power-on. Before executing the EC code loaded from a
SPI Flash Device, the MEC1322 validates the EC code
using a digital signature encoded according to PKCS
#1. The signature uses RSA-2048 encryption and
SHA-256 hashing. This provides automated detection
of invalid EC code that may be a result of malicious or
accidental corruption. It occurs before each boot of the
host processor, thereby ensuring a HW based root of
trust not easily thwarted via physical replacement
attack.
The MEC1322 is directly powered by two separate sus-
pend supply planes (VBAT and VCC1) and senses the
runtime power plane (VCC) to provide “Instant On” and
system power management functions. It also contains
an integrated VCC1 Reset Interface and a system
Power Management Interface that supports low-power
states and can drive state changes as a result of hard-
ware wake events.
DS00001719D-page 2
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