MEC1322 Datasheet, PDF (208/456 Pages) Microchip Technology – Keyboard and Embedded Controller for Notebook PC

MEC1322
15.9.4 GIRQ11
TABLE 15-14: BIT DEFINITIONS FOR GIRQ11 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[7:0] GPIO[007:000]
GPIO_Event
Y Bits[0:7] are controlled by the GPIO_Events generated by
GPIO000 through GPIO007, respectively.
[15:8] GPIO[017:010]
GPIO_Event
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
Y Bits[8:15] are controlled by the GPIO_Events generated
by GPIO010 through GPIO017, respectively.
[23:16] GPIO[027:020]
GPIO_Event
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
Y Bits[16:23] are controlled by the GPIO_Events generated
by GPIO020 through GPIO027, respectively.
[30:24] GPIO[036:030]
GPIO_Event
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
Y Bits[24:30] are controlled by the GPIO_Events generated
by GPIO030 through GPIO036, respectively.
31
n/a
15.9.5 GIRQ12
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
n/a
N See Table 15-7, "GIRQx Source Register", Table 15-8,
"GIRQx Enable Set Register", Table 15-10, "GIRQx
Enable Clear Register", and Table 15-9, "GIRQx Result
Register" for a definition of this bit for the Source, Enable,
and Result registers.
TABLE 15-15: BIT DEFINITIONS FOR GIRQ12 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
0
I2C0 / SMB0
1
I2C1 / SMB1
2
I2C2 / SMB2
SMB
SMB
SMB
N I2C/SMBus controller 0 interrupt. This interrupt is signaled
when the I2C/SMBus controller 0 asserts its interrupt
request.
N I2C/SMBus controller 1 interrupt. This interrupt is signaled
when the I2C/SMBus controller 1 asserts its interrupt
request.
N I2C/SMBus controller 2 interrupt. This interrupt is signaled
when the I2C/SMBus controller 2 asserts its interrupt
request.
DS00001719D-page 208
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