Z85233 Datasheet, PDF (97/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
Hence, on the ESCC, there is no need to wait for the 2nd
TxIP bit to set before writing data for the next packet
which reduces the overhead.
Auto EOM Reset (WR7' bit D1): As described above, the
Tx Underrun/EOM Latch has to be reset before the Trans-
mit Shift register completes shifting out the last character,
but after first character has been written. One of the ways
to reset it is for the CPU to issue the “Reset Tx Under-
run/EOM Latch” command. The other method to accom-
plish it is by the “Automatic EOM Latch Reset feature” by
setting bit D1 in WR7', which is one of the enhancements
made to the ESCC. By setting this bit to one, it eliminates
the need for the CPU command. In this mode, the CRC
generator is automatically reset at the start of every pack-
et, without the CPU command. Hence, it is not required to
reset the CRC generator prior to writing data into the ES-
CC. This is particularly valuable to a DMA driven system
where issuing CPU commands while the DMA is transfer-
ring data is difficult. Also, it is very useful if the data rate is
very high and the CPU may not be able to issue the com-
mand on time.
Auto Tx Flag (WR7' bit D0): With the NMOS/CMOS ver-
sion of the SCC, in order to accomplish Mark idle, it is re-
quired to enable the transmitter as Mark idle; then re-pro-
gram to Flag idle before writing first data, and then
reprogram again to mark idle as described above. Normal-
ly, during mark idle, the transmitter sends continuous
flags, but the ESCC can idle MARK under program control.
By setting the Mark/Flag idle bit (D3) in WR10 to 1, the
transmitter sends continuous 1s in place of the idle flags.
The closing flag always transmits correctly even when this
mode is selected. Normally, it is necessary to reset WR10
D3 to 0 before writing data for the next frame. However, on
the ESCC, if WR7' bit D0 is set to 1, an opening flag is
transmitted automatically and it is not necessary for the
CPU to turn the Mark Idle feature on and off between
frames.
Note: When this mode in not in effect (WR7' D0=0), the
Mark/Flag idle bit is clear to 0, allowing a flag to be trans-
mitted before data is written to the transmit buffer. Care
must be exercised in doing this because the continuous 1s
are transmitted eight at a time and all eight must leave the
Transmit Shift register. This allows a flag to be loaded into
it before the first data is written to the Transmit FIFO.
Auto RTS Deactivation (WR7' bit D2): Some applica-
tions require toggling the modem signal to indicate the end
of the packet. With the NMOS/CMOS version, this requires
intensive CPU support; the CPU needs time to determine
whether or not the last bit of the closing flag has left the
TxD pin. The ESCC has a new feature to deactivate the
/RTS signal when the last bit of the closing flag clears the
TxD pin.
If this feature is enabled by setting bit D2 of WR7', and when
WR5 bit D1 is reset during the transmission of a SDLC
frame, the deassertion of the /RTS pin is delayed until the
last bit of the closing flag clears the TxD pin. The /RTS pin
is deasserted after the rising edge of the transmit clock cycle
on which the last bit of the closing flag is transmitted. This
implies that the ESCC is programmed for Flag on Underrun
(WR10 bit D2=1) for the /RTS pin to deassert at the end of
the frame. (Otherwise, the deassertion occurs when the
next flag is transmitted). This feature works independently
of the programmed transmitter idle state. In Synchronous
modes other than SDLC, the /RTS pin immediately follows
the state programmed into WR5 D1. Note that if the /RTS
pin is connected to one of the general purpose inputs (/CTS
or /DCD), it can be used to generate an external status in-
terrupt when a frame is completely transmitted.
NRZI forced High after closing flag: On the
CMOS/NMOS version of the SCC in the SDLC mode of
operation with NRZI mode of encoding and mark idle
(WR10 bit D6=0, D5=1, D3=1), the state of the TxD pin af-
ter transmission of the closing flag is undetermined, de-
pending on the last data sent. With the ESCC in the same
operation mode (SDLC, NRZI, with mark idle), the TxD pin
is automatically forced High on the falling edge of the TxC
of the last bit of the closing flag, and then the transmitter
goes to the mark idle state.
There are several different ways for a transmitter to go into
the idle state. In each of the following cases, the TxD pin
is forced High when the mark idle condition is reached; da-
ta, CRC (2 bytes), flag and idle; data, flag and idle; data,
abort (on underrun) and idle; data, abort (by command)
and idle; idle, flag and command to idle mark. The force
High feature is disabled when the mark idle bit is reset
(programmed as mark idle). This feature is used in combi-
nation with the automatic SDLC opening flag transmission
feature, WR7' bit D0=1, to assure that data packets are
properly formatted. When these features are used togeth-
er, it is not necessary for the CPU to issue any commands
after sending a closing flag in combination with NRZI data
encoding. (On the NMOS/CMOS version, this is accom-
plished by channel reset, followed by re-initializing the
channel). If WR7' bit D0 is reset, like in the NMOS/CMOS
version, it is necessary to reset the mark idle bit (WR10, bit
D3) to enable flag transmission before a SDLC packet is
transmitted.
4.4.2 SDLC Receive
The receiver in the SCC always searches the receive data
stream for flag characters in SDLC mode. Ordinarily, the
receiver transfers all received data between flags to the re-
ceive data FIFO. However, if the receiver is not in Hunt
mode no data is received. The receiver is in Hunt mode
when first enabled, or the receiver is placed in Hunt mode
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