Z85233 Datasheet, PDF (54/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.5.1.2 Wait On Receive
and Low when active. When the processor attempts to
The Wait On Receive function is selected by setting D6 or read data from the Receive FIFO when it is empty, the
2 ^{WR1 to 0, D5 of WR1 to 1, and then enabling the function SCC asserts /WAIT until a character has reached the exit}
by setting D7 of WR1 to 1. In this mode, the /W//REQ pin location of the FIFO (Figure 2-26).
carries the /WAIT signal, and is open-drain when inactive
/DS or /RD
(from Rx FIFO)
Rx Character
Available _{FIFO Empty}
Character Available
/W//REQ
(=WAIT)
Figure 2-26. Wait On Receive Timing
This allows the use of a block move instruction to trans-
fer the receive data. In the case of the Z80X30, /WAIT
goes active in response to /DS going active, but only if
RR8 is being accessed and a read is attempted. In all
other cases, /WAIT remains open-drain. In the case of
the Z85X30, /WAIT goes active in response to /RD go-
ing active, but only if the receive data FIFO is being ac-
cessed, either directly or via the pointers. The /WAIT pin
is released in response to the falling edge of PCLK. De-
tails of the timing are shown in Figure 2-27.
Care must be taken when this mode is used. The /WAIT
pin stays active as long as the Receive FIFO remains emp-
ty. When the CPU access the SCC, the CPU remains in
the wait state until data gets into the Receive FIFO, freez-
ing the system.
/R TxC
1
2
PCLK
/WAIT
3
4
5•••8
9
10
11
12
13
Figure 2-27. Wait On Receive Timing
SYNC Modes
ASYNC Modes
UM010901-06
01
2-35