Z85233 Datasheet, PDF (43/317 Pages) Zilog, Inc. – The Zilog SCC Serial Communication Controller

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.4 INTERFACE PROGRAMMING (Continued)
by not generating the interrupt until after the byte has been
read and then locking the FIFO, only one status read is
necessary. A DMA can be used to do all data transfers
(otherwise, it would be necessary to disable the DMA to
allow the CPU to read the status on each byte).
Consequently, since the special condition locks the FIFO
to preserve the status, it is necessary to issue the Error
Reset command to unlock it. Only the exit location of the
FIFO is locked allowing more data to be received into the
other bytes of the Receive FIFO.
Special
Condition
Is It
Parity
(RR1 Bit 4)?
No
Is It
Overrun
(RR1 Bit 5)?
No
Is It
EOF
(RR1 Bit 7
No
Is It
Framing
(RR1 Bit 6)
Yes
Yes
Yes
Yes
No
Error Handlin
1
Error Handlin
Error Handlin
Is It
CRC Error
(RR1 Bit 6)?
No
Good Messag
1
1
1
Error Handlin
1
Reads Dat
Characte
Reset Highest IU
(WR0 - 38)
Ret
Figure 2-15. Special Conditions Interrupt Service Flow
2-24
UM010901-06
01